Abdelkarim Mercha

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

3D stacked IC demonstration using a through Silicon Via First approach

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Linear kink effect induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETS

In this paper, evidence will be provided for the existence of a new class of floating body effects, occurring in SOI and bulk MOSFETs in the linear operation regime and called here the linear kink effects (LKEs). It will be shown that for a sufficiently large front-gate voltage V/sub G/, the transconductance g/sub m/ exhibits a second peak, both for n- and p-channel devices. The effect is most pronounced for partially depleted (PD) n-MOSFETs or bulk MOSFETs at cryogenic temperatures. It occurs as well in fully depleted (FD) transistors, with the back-gate preferably biased into accumulation. Associated with the LKE in the drain current, there is a strong increase of the low-frequency noise spectral density S/sub I/. Similar as for the impact-ionization related noise overshoot, it is observed that the nature of the spectrum changes from 1/f-like to Lorentzian in the LKE region. It is finally shown that the switching off transients change their sign from negative to positive for V/sub G on/ above the LKE threshold, giving evidence for the presence of majority carriers in the film during the ON phase.

Low-frequency noise behavior of SiO/sub 2/--HfO/sub 2/ dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness

The low-frequency noise has been studied in nMOSFETs with an HfO/sub 2/--SiO/sub 2/ gate stack, for different thickness of the SiO/sub 2/ interfacial layer (IL). It is observed that the 1/f-like noise in linear operation, is about 50 times higher in the HfO/sub 2/ devices with a 0.8-nm chemical oxide IL, compared with the 4.5-nm thermal oxide reference n-channel transistors. This is shown to relate to the correspondingly higher trap density in the dielectric material. In addition, it is demonstrated that the noise rapidly reduces with increasing thickness of the IL. From the results for a 2.1-nm SiO/sub 2/ IL, it is derived that at a certain gate voltage range, electron tunneling to a defect band in the HfO/sub 2/ layer may contribute to a pronounced increase in the flicker noise.

Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs

Low-power 5 GHz LNA and VCO in 90 nm RF CMOS

The potential of 90 nm CMOS technology for low-power RF front-ends is demonstrated with fully integrated low-voltage Low-Noise Amplifiers (LNA) and Voltage-Controlled Oscillators (VCO). The 5.5 GHz LNA draws 3.5 mA from a 0.6 V supply with a measured power gain of 11.2 dB, and a 3.2 dB noise figure. The 6.3 GHz VCO has a phase noise of -118 dBc/Hz at 1 MHz offset, drawing 4.9 mA from a 1.2 V supply.

Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using both Cu Through Silicon Vias (TSV) First and cost effective solution Die-to-Wafer Hybrid Collective bonding. The Cu TSV-First process is inserted between contact and M1. The top die is thinned down to 25µm and bonded to the landing wafer by Hybrid Bonding. Measurements and simulations of the power delay trade-offs of various 3D Ring Oscillator are provided as a demonstration of the relevance of such process route and of the design/simulation capabilities.

Vertical GAAFETs for the Ultimate CMOS Scaling

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules.