Florian Dhalluin

Control of gold surface diffusion on si nanowires.

Silicon nanowires (NW) were grown by the vapor-liquid-solid mechanism using gold as the catalyst and silane as the precursor. Gold from the catalyst particle can diffuse over the wire sidewalls, resulting in gold clusters decorating the wire sidewalls. The presence or absence of gold clusters was observed either by high angle annular darkfield scanning transmission electron microscopy images or by scanning electron microscopy. We find that the gold surface diffusion can be controlled by two growth parameters, the silane partial pressure and the growth temperature, and that the wire diameter also affects gold diffusion. Gold clusters are not present on the NW side walls for high silane partial pressure, low temperature, and small NW diameters. The absence or presence of gold on the NW sidewall has an effect on the sidewall morphology. Different models are qualitatively discussed. The main physical effect governing gold diffusion seems to be the adsorption of silane on the NW sidewalls.

Si nanowire growth and characterization using a microelectronics-compatible catalyst: PtSi

Crystalline Si nanowires have been grown using a microelectronics-friendly solid-phase catalyst (PtSi) by chemical vapor deposition. Tapered growth occurs at high deposition temperatures (>700°C) due to uncatalyzed Si deposition at wire sidewalls, but this effect can be reduced at lower T (<600°C), while still maintaining reasonable growth rates (1μm∕h). Electrical testing of individual nanowires using conductive atomic force microscopy on as-grown samples demonstrates that wires are conducting with intrinsic resistivities in the 10–50Ωcm range.

Silicon nanowires: Diameter dependence of growth rate and delay in growth

We grew Si nanowires by chemical vapor deposition, via the vapor liquid solid growth, using silane as gaseous precursor and gold as catalyst. The results show that the nanowire length depends on their diameter. For nanowires with diameter under 100 nm, the length increases when diameter increases, because of an increase in the growth velocity. For the thicker diameter (d>100 nm), length decreases when diameter increases, due to an apparent incubation time which is all the higher as the diameter is high. We propose a semiempirical model combining Gibbs–Thomson effect and incubation time, which shows good agreement with the experimental data.

Direct quantification of gold along a single Si nanowire.

The presence of gold on the sidewall of a tapered, single silicon nanowire is directly quantified from core-level nanospectra using energy-filtered photoelectron emission microscopy. The uniform island-type partial coverage of gold determined as 0.42+/-0.06 (approximately 1.8 ML) is in quantitative agreement with the diameter reduction of the gold catalyst observed by scanning electron microscopy and is confirmed by a splitting of the photothresholds collected from the sidewall, from which characteristic local work functions are extracted using a model of the full secondary electron distributions.

Growth and characterization of gold catalyzed SiGe nanowires and alternative metal-catalyzed Si nanowires

The growth of semiconductor (SC) nanowires (NW) by CVD using Au-catalyzed VLS process has been widely studied over the past few years. Among others SC, it is possible to grow pure Si or SiGe NW thanks to these techniques. Nevertheless, Au could deteriorate the electric properties of SC and the use of other metal catalysts will be mandatory if NW are to be designed for innovating electronic. First, this articles focus will be on SiGe NWs growth using Au catalyst. The authors managed to grow SiGe NW between 350 and 400°C. Ge concentration (x) in Si1-xGexNW has been successfully varied by modifying the gas flow ratio: R = GeH4/(SiH4 + GeH4). Characterization (by Raman spectroscopy and XRD) revealed concentrations varying from 0.2 to 0.46 on NW grown at 375°C, with R varying from 0.05 to 0.15. Second, the results of Si NW growths by CVD using alternatives catalysts such as platinum-, palladium- and nickel-silicides are presented. This study, carried out on a LPCVD furnace, aimed at defining Si NW growth conditions when using such catalysts. Since the growth temperatures investigated are lower than the eutectic temperatures of these Si-metal alloys, VSS growth is expected and observed. Different temperatures and HCl flow rates have been tested with the aim of minimizing 2D growth which induces an important tapering of the NW. Finally, mechanical characterization of single NW has been carried out using an AFM method developed at the LTM. It consists in measuring the deflection of an AFM tip while performing approach-retract curves at various positions along the length of a cantilevered NW. This approach allows the measurement of as-grown single NWs Young modulus and spring constant, and alleviates uncertainties inherent in single point measurement.

Fabrication of high-density Si and SixGe1−x nanowire arrays based on the single step plasma etching process

Dense arrays of silicon and silicon germanium nanowires are fabricated using a top–down approach, which exploits the excellent patterning capabilities of inductively coupled plasmas. Using standard deep UV lithography on a previously deposited silicon oxide hard mask, silicon nanowires with straight and smooth sidewalls and a high aspect ratio greater than 60:1 can be obtained with SF6/O2/HBr/SiF4 plasma chemistries. The best results are obtained using Cl2/N2 high-density plasmas to pattern Si0.5Ge0.5 nanowires with an aspect ratio of 10:1.

Off axis holography of doped and intrinsic silicon nanowires: Interpretation and influence of fields in the vacuum

Intrinsic and axially modulated doped silicon nanowires (NWs) were studied by off-axis electron holography. Phase gradients in the vacuum were observed and compared to simulations of NWs with a varying charge density at the wire-oxide interface. It seems that intrinsic NWs are positively charged with a charge density around 2×1010 e.c. (electron charges) cm−2 and axially modulated doped NWs (with n-doped regions) are negatively charged with a charge density around −1×1012 e.c. cm−2. Expected fringing fields around the doped regions are incidentally observed but smaller than predicted by simulations. The effect of the surface charge on the reference wave is evaluated, and should not modify the obtained phase image.

Gold Catalyzed Silicon Nanowires: Defects in the Wires and Gold on the Wires

Silicon nanowires were grown by the vapour-liquid-solid (VLS) mechanism using gold as the catalyst and silane as the precursor. Although the crystalline quality of the wires is very high, sometimes defects can be observed. Some examples are shown. Gold clusters were observed on the lateral sides of the wires by means of scanning transmission electron microscopy (STEM), energy dispersive X-ray (EDX) analysis and scanning electron microscopy (SEM) images. An approximate calculation shows that the nanowire sidewalls are covered by one monolayer of gold during growth. De-wetting of the monolayer after growth results in a homogenous distribution of gold clusters on the lateral surfaces of the wires.

Fabrication of SiC Nanopillars by Inductively Coupled SF6/O2 Plasma

A top-down fabrication technique for nanometer scale silicon carbide (SiC) pillars has been demonstrated by using inductively coupled SF6/O2 plasma etching. At optimal etching conditions, the obtained SiC nanopillars exhibit high anisotropy features (aspect ratio ~ 6.5) with high etch depth (>7 μm). The etch characteristics of SiC nanopillars under these conditions show a high etch rate (550 nm/min) and a high selectivity (over 60 for Ni).