Thierry Chevolleau

CMOS compatible strategy based on selective atomic layer deposition of a hard mask for transferring block copolymer lithography patterns

A generic, CMOS compatible strategy for transferring a block copolymer template to a semiconductor substrate is demonstrated. An aluminum oxide (Al(2)O(3)) hard mask is selectively deposited by atomic layer deposition in an organized array of holes obtained in a PS matrix via PS-b-PMMA self-assembly. The Al(2)O(3) nanodots act as a highly resistant mask to plasma etching, and are used to pattern high aspect ratio (>10) silicon nanowires and nanopillars.

Roughening of porous SiCOH materials in fluorocarbon plasmas

Porous SiCOH materials integration for integrated circuits faces serious challenges such as roughening during the etch process. In this study, atomic force microscopy is used to investigate the kinetics of SiCOH materials roughening when they are etched in fluorocarbon plasmas. We show that the root mean square roughness and the correlation length linearly increase with the etched depth, after an initiation period. We propose that: (1) during the first few seconds of the etch process, the surface of porous SiCOH materials gets denser. (2) Cracks are formed, leading to the formation of deep and narrow pits. (3) Plasma radicals diffuse through those pits and the pore network and modify the porous material at the bottom of the pits. (4) The difference in material density and composition between the surface and the bottom of the pits leads to a difference in etch rate and an amplification of the roughness. In addition to this intrinsic roughening mechanism, the presence of a metallic mask (titanium nitride) c...

Impact of low-k structure and porosity on etch processes

The fabrication of interconnects in integrated circuits requires the use of porous low dielectric constant materials that are unfortunately very sensitive to plasma processes. In this paper, the authors investigate the etch mechanism in fluorocarbon-based plasmas of oxycarbosilane (OCS) copolymer films with varying porosity and dielectric constants. They show that the etch behavior does not depend on the material structure that is disrupted by the ion bombardment during the etch process. The smaller pore size and increased carbon content of the OCS copolymer films minimize plasma-induced damage and prevent the etch stop phenomenon. These superior mechanical properties make OCS copolymer films promising candidates for replacing current low-k dielectric materials in future generation devices.

Pattern density multiplication by direct self assembly of block copolymers: toward 300mm CMOS requirements

In this paper we investigate the possibility to reach 300mm CMOS requirements by integrating graphoepitaxy of PS-b-PMMA self-assembly. Different schemes to integrate DSA process by using 193nm dry lithography or e-Beam lithography will be presented. Moreover, several challenges like solvent compatibility, bake kinetics and defectivity will be addressed. Concerning defectivity, we will propose a methodology in order to evaluate and optimize the long range order induced by graphoepitaxy of the block copolymer DSA. This approach affords the monitoring of the overall block copolymer self-assembly process and enables us to easily optimize the parameters required for a long-range order structuration, leading to a near zero-defects block copolymers self-assembled arrays. Transfer capabilities of the PS masks in the bulk silicon substrate by using plasma-etching will be also detailed, both with the film on bare silicon or organized with graphoepitaxy approaches. These results show the high potential of DSA to be integrated directly into the conventional CMOS lithography process in order to achieve high resolution and pattern density multiplication, at a low cost.

Residue growth on metallic-hard mask after dielectric etching in fluorocarbon-based plasmas. I. Mechanisms

This work focuses on the formation of residues that grow on a metallic-hard mask after etching of porous low-k materials in fluorocarbon-based plasmas. The residue growth, which is dependent on the air exposure time after etching, causes line and via opens that strongly impact the yield performance. The different elements which could play a role in the chemical reactions have been clarified. The authors have demonstrated that in their experimental conditions, after fluorocarbon etching and air exposure, the oxidized titanium nitride reacts with fluorhydric acid to form metallic salts. This is a reaction between fluorine from the reactive layer formed on titanium nitride and hydrogen coming from the atmosphere. This reaction is all the more fast because the titanium nitride is oxidized.

Fabrication of high-density Si and SixGe1−x nanowire arrays based on the single step plasma etching process

Dense arrays of silicon and silicon germanium nanowires are fabricated using a top–down approach, which exploits the excellent patterning capabilities of inductively coupled plasmas. Using standard deep UV lithography on a previously deposited silicon oxide hard mask, silicon nanowires with straight and smooth sidewalls and a high aspect ratio greater than 60:1 can be obtained with SF6/O2/HBr/SiF4 plasma chemistries. The best results are obtained using Cl2/N2 high-density plasmas to pattern Si0.5Ge0.5 nanowires with an aspect ratio of 10:1.

Analysis of water adsorption in plasma-damaged porous low-k dielectric by controlled-atmosphere infrared spectroscopy

The integration of porous dielectric (low-k) in interconnects of integrated circuits is limited by the damage induced by plasma processes to the porous material. Plasma-damaged materials become hydrophilic, which degrades the electrical properties. However, the exact role of water is not fully understood. In this paper, the authors setup a dedicated cell to analyze water adsorption in plasma-damaged porous low-k dielectrics by infrared spectroscopy at various pressures of water vapor. The authors show that OH groups are present in the material under vacuum and that water adsorbs in the material first as icelike water and then as liquidlike water when the relative humidity is larger than ∼50%. The consequences for microelectronics applications are discussed.

Impact of Downstream Ash Plasmas on Ultra Low-k Materials

Introduction Next generation integrated circuits require novel materials with a dielectric constant lower than 2.5. To lower the dielectric constant, porous Methyl-SilsesQuioxane (MSQ) materials are introduced with a k value of about 2.2. The integration of these materials presents new processing issues, mainly due to a change in material density caused by the presence of the pores [1]. For instance, ash treatments for photoresist and residues removal are critical steps leading to dielectric properties modifications [2]. In this paper, we present the structure and properties modifications of porous and non-porous MSQ films under various downstream ash processes.

Development of plasma etching processes to pattern sub-15 nm features with PS-b-PMMA block copolymer masks: Application to advanced CMOS technology

The best strategies to transfer nanoholes formed from the self-assembly of Polystyren/Polymethylmethacrylate (PS/PMMA) based block copolymers into a silicon substrate are investigated. The authors show that specific issues are associated with the plasma etching of materials through the PS masks obtained from self-assembly. Indeed, due to the nanometric size of sub-15 nm contact holes and to their inherently high aspect ratio (>5), plasma etching processes typically used to etch SiO2 and silicon in the microelectronic industry must be revisited. In particular, processes where the etching anisotropy relies on the formation of passivation layer on the features sidewalls are not adapted to nanometric dimensions because these layers tend to fill the holes leading to etch stop issues. At the same time, the ion bombarding energy must be increased as compared to a typical process to overcome differential charging effects in high aspect-ratio nanoholes. However, by developing appropriate processes—such as synchro...

Self-assembly patterning using block copolymer for advanced CMOS technology: optimisation of plasma etching process

The best strategy to transfer nanopatterns formed from the self assembly of PS/PMMA bloc copolymers into a silicon substrate is investigated. We show that a hard mask patterning strategy combined with a plasma cure treatment of the PS mask are necessary to reproduce the PS mask pattern into the silicon with a good critical dimension control. In addition, typical silicon etching plasma condition must be revisited to allow the etching of sub-20 nm holes. These results indicate that block copolymer can be readily used as etching masks for advanced CMOS technology.