Fouad Demami

Fabrication of polycrystalline silicon nanowires using conventional UV lithography

Silicon nanowires are processed by using the sidewall spacer formation technique. This technique uses craftily a drawback of anisotropic etching to go beyond optical limits with conventional UV lithography for precision patterns. The final width of the spacer is controlled by the steepness of the etching side and by the uniformity of the wall recovering layer. In our process, a polysilicon layer is deposited by low pressure chemical vapour deposition technique on SiO2 wall network patterned by conventional UV lithography technique. Accurate control of the etching rate of the polysilicon leads to the formation of nanometric size sidewall spacers with a curvature radius below 100nm. Networks of such parallel polysilicon nanowires were electrically tested in function of temperature (530K 300K) with thermal activation EA ~ 0.3 eV

Fabrication and electrical characterization of silicon nanowires based resistors

Silicon nanowires (SiNWs) are synthesized via the Vapor-Liquid-Solid (VLS) mechanism using gold (Au) as metal catalyst and silane (SiH4) as precursor gas. Au nanoparticles are employed as liquid droplets catalysis during the SiNWs growth performed in a hot wall LPCVD reactor at 480°C and 40 Pa. SiNWs local synthesis at micron scale is demonstrated using classical optical photolithography process. SiNWs grow with high density anchored at the dedicated catalyst islands. This resulting network is used to interconnect two heavily doped polysilicon interdigitated electrodes leading to the formation of electrical resistors in a coplanar structure. Current-voltage (I-V) characteristics highlight a symmetric shape. The temperature dependence of the electrical resistance is activated, with activation energy of 0.47 eV at temperatures greater than 300K.