Laurent Pichon

Step-gate polysilicon nanowires field effect transistor compatible with CMOS technology for label-free DNA biosensor

Currently, detection of DNA hybridization using fluorescence-based detection technique requires expensive optical systems and complex bioinformatics tools. Hence, the development of new low cost devices that enable direct and highly sensitive detection stimulates a lot of research efforts. Particularly, devices based on silicon nanowires are emerging as ultrasensitive electrical sensors for the direct detection of biological species thanks to their high surface to volume ratio. In this study, we propose innovative devices using step-gate polycrystalline silicon nanowire FET (poly-Si NW FETs), achieved with simple and low cost fabrication process, and used as ultrasensitive electronic sensor for DNA hybridization. The poly-SiNWs are synthesized using the sidewall spacer formation technique. The detailed fabrication procedure for a step-gate NWFET sensor is described in this paper. No-complementary and complementary DNA sequences were clearly discriminated and detection limit to 1 fM range is observed. This first result using this nano-device is promising for the development of low cost and ultrasensitive polysilicon nanowires based DNA sensors compatible with the CMOS technology.

Fabrication of polycrystalline silicon nanowires using conventional UV lithography

Silicon nanowires are processed by using the sidewall spacer formation technique. This technique uses craftily a drawback of anisotropic etching to go beyond optical limits with conventional UV lithography for precision patterns. The final width of the spacer is controlled by the steepness of the etching side and by the uniformity of the wall recovering layer. In our process, a polysilicon layer is deposited by low pressure chemical vapour deposition technique on SiO2 wall network patterned by conventional UV lithography technique. Accurate control of the etching rate of the polysilicon leads to the formation of nanometric size sidewall spacers with a curvature radius below 100nm. Networks of such parallel polysilicon nanowires were electrically tested in function of temperature (530K 300K) with thermal activation EA ~ 0.3 eV

Growth-in-place deployment of in-plane silicon nanowires

Up-scaling silicon nanowire (SiNW)-based functionalities requires a reliable strategy to precisely position and integrate individual nanowires. We here propose an all-in-situ approach to fabricate self-positioned/aligned SiNW, via an in-plane solid-liquid-solid growth mode. Prototype field effect transistors, fabricated out of in-plane SiNWs using a simple bottom-gate configuration, demonstrate a hole mobility of 228 cm2/V s and on/off ratio >103. Further insight into the intrinsic doping and structural properties of these structures was obtained by laser-assisted 3 dimensional atom probe tomography and high resolution transmission electron microscopy characterizations. The results could provide a solid basis to deploy the SiNW functionalities in a cost-effective way.

Variable range hopping conduction in N- and P-type in situ doped polycrystalline silicon nanowires

Temperature dependence of electrical properties in N- and P-type in situ doped polycrystalline silicon nanowires synthesized by the sidewall spacer formation technique has been studied. Experimental analysis has been carried out for a temperature range from 200xa0K to 530xa0K on in situ doped polycrystalline silicon nanowires with doping level varying from 2xa0×xa01016xa0to 9xa0×xa01018xa0cm−3. Results show that for N- and P-type doped samples the temperature dependence of the conductivity follows the 3D variable range hopping model due to hopping between localized electronic states near the Fermi level. The corresponding densities of states are determined following exponential (tail states) distributions associated to the statistical shift of the Fermi level.

Fabrication and electrical characterization of silicon nanowires based resistors

Silicon nanowires (SiNWs) are synthesized via the Vapor-Liquid-Solid (VLS) mechanism using gold (Au) as metal catalyst and silane (SiH4) as precursor gas. Au nanoparticles are employed as liquid droplets catalysis during the SiNWs growth performed in a hot wall LPCVD reactor at 480°C and 40 Pa. SiNWs local synthesis at micron scale is demonstrated using classical optical photolithography process. SiNWs grow with high density anchored at the dedicated catalyst islands. This resulting network is used to interconnect two heavily doped polysilicon interdigitated electrodes leading to the formation of electrical resistors in a coplanar structure. Current-voltage (I-V) characteristics highlight a symmetric shape. The temperature dependence of the electrical resistance is activated, with activation energy of 0.47 eV at temperatures greater than 300K.

Experimental validation of the exponential localized states distribution in the variable range hopping mechanism in disordered silicon films

Carriers transport in low temperature (≤600u2009°C) polycrystalline silicon thin film transistor channel region is studied for devices biased from weak to strong inversion. Analysis is supported by the theory of the 3D variable range hopping model due to hopping between localized electronic states near the Fermi level. The corresponding density of states is determined following an exponential (tail states) distribution associated with the statistical shift of the Fermi level.

Optimization of silica deposition by sputtering in the silicon thin film transistors realization in low temperature technology

Abstract This paper gives some optical and electrical characteristics of silicon dioxide thin films obtained by magnetron sputtering. The aim of these films is to serve as gate insulator of MOS transistors with poly-Si active semiconductor. As-deposited thin films with properties close to the ones obtained by other methods, including thermal oxidation, however, present, in some cases, important leakage currents, which can be reduced by annealing.