Régis Rogel

Analysis of the activation energy of the subthreshold current in laser- and solid-phase-crystallized polycrystalline silicon thin-film transistors

Analysis of the thermal and gate-voltage dependences of the current in the subthreshold region is performed on both low-temperature laser-crystallized and solid-phase-crystallized polycrystalline silicon (polysilicon) thin-film transistors (TFTs). Temperature measurements are made at first in order to extract the variations of the activation energy EA of the drain current with the gate voltage. The plot of the subthreshold current versus the measured activation energy leads to an apparent activation energy EA/n, where the n factor is extracted from the slope of this plot. The n factor is close to 1 for laser-crystallized polysilicon TFTs while it is rather close to 2 for solid-phase-crystallized ones. These two values can be attributed to a different defect distribution in the two differently crystallized TFTs polysilicon active layers.

Step-gate polysilicon nanowires field effect transistor compatible with CMOS technology for label-free DNA biosensor

Currently, detection of DNA hybridization using fluorescence-based detection technique requires expensive optical systems and complex bioinformatics tools. Hence, the development of new low cost devices that enable direct and highly sensitive detection stimulates a lot of research efforts. Particularly, devices based on silicon nanowires are emerging as ultrasensitive electrical sensors for the direct detection of biological species thanks to their high surface to volume ratio. In this study, we propose innovative devices using step-gate polycrystalline silicon nanowire FET (poly-Si NW FETs), achieved with simple and low cost fabrication process, and used as ultrasensitive electronic sensor for DNA hybridization. The poly-SiNWs are synthesized using the sidewall spacer formation technique. The detailed fabrication procedure for a step-gate NWFET sensor is described in this paper. No-complementary and complementary DNA sequences were clearly discriminated and detection limit to 1 fM range is observed. This first result using this nano-device is promising for the development of low cost and ultrasensitive polysilicon nanowires based DNA sensors compatible with the CMOS technology.

High mobility thin film transistors by Nd:YVO4-laser crystallization

Abstract Laser crystallization of amorphous silicon is one of the most interesting ways to obtain high-quality polycrystalline silicon films on glass. We crystallized the channel region of n- and p-type thin film transistors (TFTs) with a frequency-doubled Nd:YVO 4 laser utilizing a sequential lateral solidification process. The high repetition rate of the laser of up to 100 kHz allows for high scanning speeds of up to 5 cm s −1 . The laser irradiation was performed in air at room temperature. The resulting polycrystalline films showed longitudinally elongated grains with a length of up to 100 μm in the scanning direction of the laser beam and a width of up to 2 μm perpendicular to the scanning direction. Due to the anisotropic grain dimensions, the TFT performance depends on the orientation of the channel with respect to the scanning direction. Furthermore, a scale down of the TFT dimensions results in a better device performance because the number of grain boundaries within the channel of a TFT is reduced. For example, a decrease in the width W and length L of the channel from W =63 and L =22 μm to W =30 and L =15 μm increases the field-effect electron mobility μ N of the TFTs from μ N =410 to 510 cm 2 V −1 s −1 . The high mobility μ and low sub-threshold slope S =0.45 V decade −1 obtained with a gate oxide thickness of 100 nm show the high quality of laser-crystallized polycrystalline silicon.

Transport mechanisms in hydrogenated microcrystalline silicon

Transport properties of microcrystalline (μc-Si/H) and polycrystalline (p-Si) silicon films are analyzed by time resolved microwave conductivity (TRMC), diffusion-induced TRMC (DTRMC), and Hall measurements. The comparison of carrier mobilities in microcrystalline silicon determined by TRMC as well as DTRMC shows that trapping in the disordered part of these films is not the main limiting parameter for transport in microcrystalline silicon. Besides, it is demonstrated that TRMC measurements are not sensitive to barriers between the crystallites. Our measurements reveal that, contrary to the case of p-Si, the influence of barriers in μc-Si/H can be neglected. Transport in μc-Si/H is consequently mainly limited by defects inside the crystallites.

Fabrication of polycrystalline silicon nanowires using conventional UV lithography

Silicon nanowires are processed by using the sidewall spacer formation technique. This technique uses craftily a drawback of anisotropic etching to go beyond optical limits with conventional UV lithography for precision patterns. The final width of the spacer is controlled by the steepness of the etching side and by the uniformity of the wall recovering layer. In our process, a polysilicon layer is deposited by low pressure chemical vapour deposition technique on SiO2 wall network patterned by conventional UV lithography technique. Accurate control of the etching rate of the polysilicon leads to the formation of nanometric size sidewall spacers with a curvature radius below 100nm. Networks of such parallel polysilicon nanowires were electrically tested in function of temperature (530K 300K) with thermal activation EA ~ 0.3 eV

Growth-in-place deployment of in-plane silicon nanowires

Up-scaling silicon nanowire (SiNW)-based functionalities requires a reliable strategy to precisely position and integrate individual nanowires. We here propose an all-in-situ approach to fabricate self-positioned/aligned SiNW, via an in-plane solid-liquid-solid growth mode. Prototype field effect transistors, fabricated out of in-plane SiNWs using a simple bottom-gate configuration, demonstrate a hole mobility of 228 cm2/V s and on/off ratio >103. Further insight into the intrinsic doping and structural properties of these structures was obtained by laser-assisted 3 dimensional atom probe tomography and high resolution transmission electron microscopy characterizations. The results could provide a solid basis to deploy the SiNW functionalities in a cost-effective way.

Fabrication and electrical characterization of silicon nanowires based resistors

Silicon nanowires (SiNWs) are synthesized via the Vapor-Liquid-Solid (VLS) mechanism using gold (Au) as metal catalyst and silane (SiH4) as precursor gas. Au nanoparticles are employed as liquid droplets catalysis during the SiNWs growth performed in a hot wall LPCVD reactor at 480°C and 40 Pa. SiNWs local synthesis at micron scale is demonstrated using classical optical photolithography process. SiNWs grow with high density anchored at the dedicated catalyst islands. This resulting network is used to interconnect two heavily doped polysilicon interdigitated electrodes leading to the formation of electrical resistors in a coplanar structure. Current-voltage (I-V) characteristics highlight a symmetric shape. The temperature dependence of the electrical resistance is activated, with activation energy of 0.47 eV at temperatures greater than 300K.

Hall effect magnetic sensors based on polysilicon TFTs

This paper deals with magnetic position sensors compatible with large-area electronics using polycrystalline silicon deposited by a low-pressure chemical reaction technique. The principle of this large-area position sensor is a matrix of thin-film field effect transistors (TFTs) with two additional Hall probes. The performances of the TFT-based cells are linked to the crystalline quality of the active polysilicon layer, which depends on the deposition conditions and on technological processes. Layers are made from two precursor gases, silane or disilane, and two processes. We have compared the sensitivity (absolute or relative) of devices and measured their power consumption. Sensors made from disilane have a sensitivity of 18 mV/T, and the ones made with a monolayer process a sensitivity of 28 mV/T. We propose a simple model, which describes the bias dependency of the sensitivity. The effect of geometry and layer morphology on the offset voltage is also studied.

High quality unhydrogenated low-pressure chemical vapor deposited polycrystalline silicon

Abstract Intrinsic amorphous silicon (a-Si) is deposited at 550°C and at different pressures using low-pressure chemical vapor deposition (LPCVD) technique. These deposition pressures (90, 150 and 200 Pa) were obtained by pushing back the powder regime formation that occurred around 90 Pa. Using kinetics of solid phase crystallization monitored by in situ measurements of the film conductance, optical transmission, dark conductivity vs temperature, Hall effect, and photoconductivity under monochromatic light were measured to determine the properties of crystallized films; we show that device quality is obtained at larger deposition pressure above which the powder formation regime begins. Particularly, the largest Hall mobility known to us of undoped polycrystalline silicon (polysilicon) (40 cm 2 /V s) is reported. Moreover at this larger deposition pressure, a deposition rate of 0.8 μm/h is obtained. This rate is the largest obtained by LPCVD of a-Si to our knowledge. The improvements of some electrical properties of the polycrystalline films are explained in terms of a high pressure relaxed a-Si network.

Experimental validation of the exponential localized states distribution in the variable range hopping mechanism in disordered silicon films

Carriers transport in low temperature (≤600 °C) polycrystalline silicon thin film transistor channel region is studied for devices biased from weak to strong inversion. Analysis is supported by the theory of the 3D variable range hopping model due to hopping between localized electronic states near the Fermi level. The corresponding density of states is determined following an exponential (tail states) distribution associated with the statistical shift of the Fermi level.