Francesc Moll

Review of energy harvesting techniques and applications for microelectronics

The trends in technology allow the decrease in both size and power consumption of complex digital systems. This decrease in size and power gives rise to new paradigms of computing and use of electronics, with many small devices working collaboratively or at least with strong communication capabilities. Examples of these new paradigms are wearable devices and wireless sensor networks. Currently, these devices are powered by batteries. However, batteries present several disadvantages: the need to either replace or recharge them periodically and their big size and weight compared to high technology electronics. One possibility to overcome these power limitations is to extract (harvest) energy from the environment to either recharge a battery, or even to directly power the electronic device. This paper presents several methods to design an energy harvesting device depending on the type of energy avaliable.

Optimum Piezoelectric Bending Beam Structures for Energy Harvesting using Shoe Inserts

The small amount of power demanded by many present-day electronic devices opens up the possibility to convert part of the energy present in the environment into electrical energy, using several methods. One such method is to use piezoelectric film-bending beams inside a shoe, and use part of the mechanical energy employed during normal walking activity. This study analyzes several bending beam structures suitable for the intended application (shoe inserts and walking-type excitation) and obtains the resulting strain for each type as a function of their geometrical parameters and material properties. As a result, the optimum configuration can be selected.

Noise generation and coupling mechanisms in deep-submicron ICs

On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques depends on the circuit, its implementation, and the possible physical failures and parasitic coupling models. This new demand for test technology practices precipitated the investigation of dl/dt and dV/dt noise generation and propagation mechanisms.

Methodology of detection of spurious signals in VLSI circuits

The continuous reduction in scale achieved in microelectronic technology and the increasing switching speed may cause parasitic or spurious signals to appear, due to crosstalk. In this work, scale reduction of interconnections is analyzed, showing the increasing mutual capacitance and a model of crosstalk considering parasitic capacitive coupling is shown. A method for studying the propagation of crosstalk signals has been developed for combinational circuits. An algorithm for crosstalk faults test pattern generation is proposed taking into account the propagation limitation of the signals. Experimental results are shown.<<ETX>>

VCTA: A Via-Configurable Transistor Array regular fabric

Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity must be pushed to the limit to deal with severe systematic process variations in future technology nodes. With this objective, we propose and evaluate a new regular layout style called Via-Configurable Transistor Array (VCTA) that maximizes regularity at device and interconnect levels. In order to assess VCTA maximum layout regularity tradeoffs, we implement 32-bit adders in the 90 nm technology node for VCTA and compare them with implementations that make use of standard cells. For this purpose we study the impact of photolithography proximity and coma effects on channel length variations, and the impact of shallow trench isolation mechanical stress on threshold voltage variations. We demonstrate that both variations, that are important sources of energy and delay circuit variability, are minimized through VCTA regularity.

System-Level Simulation of a Self-Powered Sensor with Piezoelectric Energy Harvesting

This paper presents a complete system simulation of a self-powered communication module. The components are described with the Verilog-A language, that allows to merge the electrical and mechanical models of the system. The self-powered sensor system is composed by an energy harvesting piezoelectric generator that powers a RF transmitter. The simulations here presented compare between the case of a battery-less and battery-powered system. The results obtained with the simulation model implemented allow to show how design choices of the system change the periodicity of the transmission and the ability to recharge the battery.

Crosstalk effects between metal and polysilicon lines in CMOS integrated circuits

In this work the problem of crosstalk between a metal and a polysilicon line is considered. The polysilicon line is modeled as an RC distributed transmission line, and the metal fine is considered as a single node capacitively coupled to the polysilicon line. The voltage response in the polysilicon line to a step transition in the metal line is calculated, and the influence of geometrical aspects, resistance of polysilicon, and evolution of waveform with distance from the drivers end of the poly line are investigated. >

Analysis of dissipation energy of switching digital CMOS gates with coupled outputs

The current trend of a high level of integration causes an important parasitic coupling between lines, that is, a capacitance between lines exists in addition to capacitance to ground. This paper calculates how this coupling capacitance influences the power consumption, taking into account the value of the capacitance, the switching activity of the coupled lines, and the influence of relative delay between transitions in the coupled lines.

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core contribution is a detailed-routing algorithm based on a Boolean formulation of the problem. The algorithm uses a novel encoding scheme, graph theory to support floating terminals, efficient heuristics to reduce the computational cost, and minimization of the number of unconnected pins in case the cell is unroutable. The versatility of the algorithm is demonstrated by routing single- and double-height cells. The efficiency is ascertained by synthesizing a library with 127 cells in about one hour and a half of CPU time. The layouts derived by the implemented tool have also been compared with the ones from a commercial library; thus, showing the competitiveness of the approach for gridded geometries.

Pespectives of TFET devices in ultra-low power charge pumps for thermo-electric energy sources

The superior electrical characteristics of the heterojunction III-V Tunnel FET (TFET) devices can outperform current technologies in the process of energy harvesting conversion at ultra-low power supply voltage operation (sub-0.25 V). In this work, it is shown by simulations that a cross-coupled switched-capacitor topology with GaSb-InAs TFET devices present better conversion performance compared to the use of Si FinFET technology at low temperature variations (ΔT <; 3 °C) when considering a thermo-electric energy harvesting source (with α = 80 mV/K). At higher ΔT, the conversion process is degraded with the increase of the transistor losses. Considering a ΔT of 1 °C (2 °C), one cross-coupled stage with TFET devices can achieve 74 % (69 %) of power conversion efficiency when considering an output load of 0.4 μA (6 μA). At the same conditions, the FinFET charge pump is shown inefficient.