Esteve Amat

Channel Hot-Carrier Degradation in Short-Channel Transistors With High-

Channel hot-carrier (CHC) degradation in nMOS transistors is studied for different SiO₂/HfSiON dielectric stacks and compared to SiO₂. We show that, independent of the gate dielectric, in short-channel transistors, the substrate current peak (used as a measure for the highest degradation) is at V_G = V_D, whereas for longer channels, the maximum peak is near V_G = V_D/2. We demonstrate that this shift in the most damaging CHC condition is not caused by the presence of the high- k layer but by short-channel effects. Furthermore, the CHC lifetime of short-channel transistors was evaluated at the most damaging condition V_G = V_D, revealing sufficient reliability and even larger operating voltages for the high-k stacks than for the SiO₂ reference.

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In this paper, a comprehensive study of hot- carrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate fabricated on n-type germanium-on-silicon (Ge-on-Si) substrates. Negative bias temperature instability (NBTI) has also been explored on the same devices. The following are found: (1) Impact ionization rate in Ge-on-Si MOSFETs is approximately two orders higher as compared to their Si counterpart; (2) NBTI degradation is a lesser concern than HCI for Ge-on-Si pMOSFETs; and (3) increasing the Si-passivation thickness from four to eight monolayers provides a remarkable lifetime improvement.

/Metal Gate Stacks

Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded SRAM memories. This work introduces a novel version that modifies and enhances the advantages of this method by considering the process variability impact on the memory components. Our results show between 30% and 45% SRAM lifetime increases over the existing proactive reconfiguration technique and between 1.7X and ~10X improvement over the non-proactive reconfiguration.

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

The demand for highly scalable and low power memory has led to research in emerging technologies and devices. Among these devices, memristors has attracted increased attention as being a promising storage device. However, due to its nano-scale size it faces various types of reliability issues. In this study, we have reviewed the memristive mechanisms and reliability concerns existing in memristor memory design. Then, we have simulated the ionic drift memristor model in presence of the process variability. Next, by considering a normal distribution for the resistive distribution of memristors in LRS and HRS state we have shown the instabilities and probability of failure in read and write procedure of memristive memories, and highlighted the requisite and motivation for the reliability aware memristive circuit design.

Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime

Abstract The substitution of the SiO2 gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO2 thickness. To improve the quality of the high-k/Si interface a very thin SiO2 film is grown between both materials. In this work, HfO2/SiO2 stacks with different SiO2 thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO2 in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO2 interfacial layer influences the advanced stages of the stack degradation.

Reliability challenges in design of memristive memories

The degradation of NMOS and PMOS transistors within CMOS inverters has been analyzed. Channel-hot-carrier (CHC) degradation and/or bias temperature instabilities (BTIs) are identified as aging mechanisms, and their implications at the device and circuit levels are discussed. Device- and circuit-level results have been linked using the BSIM4 SPICE model.

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

In ultrascaled complimentary metal-oxide-semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (SiO2 or high- k). A new model to describe the CHC degradation behavior in n-channel metal-oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and short-channel transistors with high- k or SiO2 as a dielectric.

Channel-Hot-Carrier Degradation and Bias Temperature Instabilities in CMOS Inverters

It has been stated that 3T1D-DRAM cell is a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by variability. In this paper, it is shown that the 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation when they are scaled to nodes smaller than 22 nm. Furthermore, we present some strategies to mitigate the cell variability. Moreover, while scaling down capacitorless DRAM cells is a challenging trend, we also show how the scaling drawbacks can be compensated through the following: 1) the channel strain of the cell devices and 2) the proposal of new strategies to further enhance the memory cell behavior.

Gate Voltage Influence on the Channel Hot-Carrier Degradation of High-

Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.

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In this paper, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFETs, and III-V MOSFETs), and subjected to different reliability scenarios (variability and soft errors). FinFET-based circuits show the highest robustness against variability and soft error environments.