Francesco A. Amoroso

Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier

This work focuses on the subthreshold design of ultra low-voltage low-power operational amplifiers. A well-defined procedure for the systematic design of subthreshold operational amplifiers op-amps is introduced. The design of a 0.5-V two-stage Miller-compensated amplifier fabricated with a 0.18-µm complementary metal-oxide-semiconductor process is presented. The op-amp operates with all transistors in subthreshold region and achieves a DC gain of 70dB and a gain-bandwidth product of 18kHz, dissipating just 75nW. The active area of the chip is i¾?0.057mm2. Experimental results demonstrate that well-designed subthreshold op-amps are a very attractive solution to implement sub-1-V energy-efficient applications for modern portable electronic systems. A comparative analysis with low-voltage, low-power op-amp designs available in the literature highlights that subthreshold op-amps designed according to the proposed design procedure achieve a better trade-off among speed, power, and load capacitance. Copyright

Settling Time Optimization for Three-Stage CMOS Amplifier Topologies

A new settling-time-oriented design methodology for the most common three-stage operational amplifier (op-amp) schemes reported in the literature is presented in this paper. The proposed approach allows the systematic sizing of the compensation network in order to reach the best closed-loop op-amp settling behavior. To demonstrate the effectiveness of the methodology and the correctness of the analysis, the examined three-stage op-amp topologies are designed in a commercial 0.35-¿m CMOS technology. Circuit simulations show that the proposed design approach, for each investigated topology, guarantees a significant settling time reduction with respect to the compensation network sizing strategies proposed in the past. An ad-hoc figure of merit, which evaluates the trade-off between the settling time, the load capacitance and the total op-amp stage transconductances, is also defined in order to estimate the op-amp efficiency in terms of time-domain performances.

Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances

The impact of high-order integrator dynamics on switched-capacitor sigma-delta modulator (¿¿M) performances is investigated in this paper. An advanced generic integrator-settling model to take into account high-order dynamic effects is presented and validated by means of transistor-level simulations of circuits implemented in a commercial 0.35 ¿m CMOS technology. The model is used through the paper to carry out an exhaustive behavioral analysis for second-order single-bit ¿¿Ms characterized by first-, second-, and third-order integrator dynamics, showing how high-order poles and zeros can affect the ¿¿M characteristics remarkably. The proposed analysis provides useful guidelines to fix a convenient integrator poles/zeros placement in order to achieve an effective ¿¿M design flow.

Design considerations for fast-settling two-stage Miller-compensated operational amplifiers

The settling behavior of two-stage Miller-compensated operational amplifiers (op-amps) is investigated in this paper. The analysis aims to evaluate the real effectiveness of conventional design approaches for the settling performances optimization when op-amps are used in common SC circuits. It is shown that the existing strategies are effective only for sufficiently large values of the load capacitance to be driven by the SC circuit. In typical situations in which this condition is not satisfied, the conventional design rules to fix the element of the op-amp compensation network may be inadequate to achieve fast-settling two-stage amplifiers. Design examples in a commercial 0.35-µm CMOS technology demonstrate that a careful strategy for the sizing of the amplifier compensation network elements can result in a significant reduction of the op-amp settling time with respect to designs in which the conventional criterion is used.

Settling-time-oriented design procedure for two-stage amplifiers with current-buffer Miller compensation

A novel design procedure for two-stage operational amplifiers (op-amps) with current-buffer Miller compensation (CBMC) is proposed. The method is based on equations which relate both bias current and aspect ratio of transistors to the main amplifier parameters. The important innovation of the procedure is the definition of a systematic strategy to achieve the desired settling time by performing the op-amp dynamic behaviour optimization, which is badly needed in high-performance discrete-time applications. To prove the effectiveness of the proposed approach, a design example of a CBMC op-amp in 0.35 mum CMOS technology is presented.

A new efficient SC integrator scheme for high-speed low-power applications

A new solution to implement efficient switched-capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35−µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright

Potentiality of variable-rate PEVs charging strategies for smart grids

The diffusion of Plug-in Electric Vehicles (PEVs), is expected to increase considerably over the next few years. Ad-hoc charging systems interacting in real-time with smart grids will be needed increasingly to overcome the severe overload problems in electric distribution grids caused by the huge demand for energy to charge a large number of vehicles. These systems will have to implement the scheduling of the charging process on the basis of negotiation phases between the user and the electric utility in which information about fares, amount of required energy and maximum time available for completing the charging before user drive off are exchanged. Possible smart energy dispatching strategies which take advantage of varying the charging rate during the charging process are analyzed in the paper. As shown, the adoption of a variable charging rate is a very promising solution for developing ad-hoc algorithms to fully exploit the distribution grid capacity, allowing higher customer satisfaction and utility financial profits to be reached with respect to algorithms based on fixed charging rate. The results of the analysis performed give useful guidelines for the development of smart-grid management policies and for the design of next-generation PEVs battery chargers.

Large-signal settling optimization of SC circuits using two-stage amplifiers with current-buffer miller compensation

The large-signal performances of switched-capacitor (SC) circuits employing two-stage operational amplifiers (opamps) with current-buffer Miller compensation are analyzed. Well-defined rules to fix carefully the bias currents of the two op-amp stages are proposed in order to optimize the amplifier settling behavior. Simulation results related to op-amps designed in a commercial 0.35 µm CMOS technology show the usefulness of the proposed design guidelines.

Design approach for high-bandwidth low-power three-stage operational amplifiers

A new design approach to optimize the frequency compensation network of three-stage operational amplifiers (op-amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well-established three-stage op-amps using Nested-Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35-µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op-amps. It is also demonstrated that NMCFNR op-amps, designed according to the proposed method, even guarantee larger values of the gain-bandwidth product than three-stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping-factor control frequency compensation. Copyright

Design criterion for high-speed low-power SC circuits

The settling behavior of switched-capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two-stage Miller-compensated operational amplifiers (op-amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op-amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35- µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright