Felice Crupi

Reliability issues in MuGFET nanodevices

In this paper we review some recent results on reliability of MuGFET nanodevices with different gate stacks, including polycrystalline-Si/SiON as well as deposited metal gate/high-k stacks. In the first part we show how we can get information on the interface quality of the sidewall and top interface of the devices, by using an adapted charge pumping technique on gated diode structures. Then we compare the TDDB behavior of MuGFET and planar devices and we will show that if adequate processing is used, the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown for different gate voltages and temperatures. Next we discuss the Bias Temperature Instability (BTI) behavior of MuGFET CMOS devices. Novel interface passivation techniques as well as the impact of different dielectric nitridation techniques on BTI are discussed, showing similar BTI dependence on Nitrogen incorporated in MuGFET dielectrics as in planar devices. Finally we also discuss the ESD performance of MuGFET devices and we demonstrate that reasonable intrinsic ESD performance can be obtained, but achieving this desired ESD-robustness is found to be critically dependent on various design and process parameters. As a result the design of ESD protection for FinFET technology appears to be a challenging task for the future.

Low-frequency (1/f) noise behavior of locally stressed HfO/sub 2//TiN gate-stack pMOSFETs

The low-frequency noise behavior of locally strained pMOSFETs with a 7HfO/sub 2//TiN gate stack is reported. Different ways of compressive-strain engineering have been compared: a Si/sub 3/N/sub 4/ cap layer, SiGe source/drain (S/D) regions, or the combination of both. It is shown that the use of a cap layer does not degrade the 1/f noise magnitude, while an increase of this parameter is found for SiGe S/D devices. This increase is ascribed to the creation of additional traps in the high-k oxide by the SiGe S/D processing. The effect appears to be independent of the germanium content in the range studied (15%-25%). Another conclusion is that no direct correlation has been observed here between the applied stress and the noise magnitude.

High-mobility 0.85nm-EOT Si 0.45 Ge 0.55 -pFETs: Delivering high performance at scaled VDD

This work demonstrates the successful integration of 0.85nm-EOT Si<inf>0.45</inf>Ge<inf>0.55</inf>-pFETs using a gate first approach. An in-depth analysis, ranging from capacitor-level up to circuit-level is carried out, with systematic benchmarking to a conventional Si-channel reference. Outperforming the state-of-the-art Si<inf>0.55</inf>Ge<inf>0.45</inf>-pFETs, an I<inf>ON</inf> of 630µA/µm at L<inf>G_POLY</inf> = 35nm with I<inf>OFF</inf> = 100nA/µm and V<inf>DD</inf> = −1V has been achieved without any epi-S/D boosters. Significant improvements at lower V<inf>DD</inf> have also been confirmed through complex circuit simulations and validated by experimental results.

Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

a imec, Kapeldreef 75, 3001 Heverlee, Belgium b ESAT-INSYS department, Katholieke Universiteit Leuven, 3000 Leuven, Belgium c also Post-doctoral fellow of the Fund for Scientific Research-Flanders (FWO), 1000 Brussels, Belgium d also IWT-Vlaanderen, 1000 Brussels, Belgium e Sony assignee at imec, 3001 Leuven, Belgium f Currently at IBM g Universita della Calabria, Arcavacata di Rende, Italy h Panasonic assignee at imec, 3001 Leuven, Belgium