Giuseppe Iannaccone

Electronics based on two-dimensional materials

The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industrys quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Design criteria for the RF section of UHF and microwave passive RFID transponders

A set of design criteria for the radio-frequency (RF) section of long-range passive RF identification (RFID) transponders operating in the 2.45-GHz or 868-MHz industrial, scientific, and medical (ISM) frequency ranges is derived in this paper, focusing in particular on the voltage multiplier, the power-matching network, and the backscatter modulation. The paper discusses the design tradeoffs between the error probability at the reader receiver and the converted RF-dc power at the transponder, determining the regions of the design space that allow optimization of the operating range and the data rate of the RFID system.

Simulation of Graphene Nanoribbon Field-Effect Transistors

We present an atomistic 3-D simulation of graphene nanoribbon field-effect transistors (GNR-FETs), based on the self consistent solution of the 3-D Poisson and Schrodinger equations with open boundary conditions within the nonequilibrium Greens function formalism and a tight-binding Hamiltonian. With respect to carbon nanotube FETs, GNR-FETs exhibit comparable performance, reduced sensitivity to the variability of channel chirality, and similar leakage problems due to band-to-band tunneling. Acceptable transistor performance requires prohibitive effective nanoribbon width of 1-2 nm and atomistic precision that could in principle be obtained with periodic etch patterns or stress patterns.

A Sub-1-V, 10 ppm/

An extreme low power voltage reference generator operating with a supply voltage ranging from 0.9 to 4 V has been implemented in AMS 0.35-mum CMOS process. The maximum supply current measured at the maximum supply voltage and at 80degC is 70 nA. A temperature coefficient of 10 ppm/degC is achieved as the combined effect of 1) a perfect suppression of the temperature dependence of mobility; 2) the compensation of the channel length modulation effect on the temperature coefficient; and 3) the absence of the body effect. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -53 and -42 dB, respectively. The occupied chip area is 0.045 mm2.

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A voltage reference circuit operating with all transistors biased in weak inversion, providing a mean reference voltage of 257.5 mV, has been fabricated in 0.18 m CMOS technology. The reference voltage can be approximated by the difference of transistor threshold voltages at room temperature. Accurate subthreshold design allows the circuit to work at room temperature with supply voltages down to 0.45 V and an average current consumption of 5.8 nA. Measurements performed over a set of 40 samples showed an average temperature coefficient of 165 ppm/ C with a standard deviation of 100 ppm/ C, in a temperature range from 0 to 125°C. The mean line sensitivity is ≈0.44%/V, for supply voltages ranging from 0.45 to 1.8 V. The power supply rejection ratio measured at 30 Hz and simulated at 10 MHz is lower than -40 dB and -12 dB, respectively. The active area of the circuit is ≈0.043mm2.

C, Nanopower Voltage Reference Generator

In this letter, we propose the bilayer graphene tunnel field-effect transistor (TFET) as a device suitable for fabrication and circuit integration with present-day technology. It provides high I on/I off ratio at ultralow supply voltage, without the limitations in terms of prohibitive lithography and patterning requirements for circuit integration of graphene nanoribbons. Our investigation is based on the solution of the coupled Poisson and Schrodinger equations in three dimensions, within the non-equilibrium Greens function formalism on a tight binding Hamiltonian. We show that the small achievable gap of only few hundreds of millielectronvolts is still enough for promising TFET operation, providing a large I on/I off ratio in excess of 103 even for a supply voltage of only 0.1 V. A key to this performance is the low quantum capacitance of bilayer graphene, which permits to obtain an extremely small subthreshold swing S smaller than 20 mV/dec at room temperature.

A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference

We present an atomistic 3-D simulation study of the performance of graphene-nanoribbon (GNR) Schottky-barrier field-effect transistors (SBFETs) and transistors with doped reservoirs (MOSFETs) by means of the self-consistent solution of the Poisson and Schrodinger equations within the nonequilibrium Greens function (NEGF) formalism. Ideal MOSFETs show slightly better electrical performance for both digital and terahertz applications. The impact of nonidealities on device performance has been investigated, taking into account the presence of single vacancy, edge roughness, and ionized impurities along the channel. In general, MOSFETs show more robust characteristics than SBFETs. Edge roughness and single-vacancy defect largely affect the performance of both device types.

Ultralow-Voltage Bilayer Graphene Tunnel FET

Reducing energy consumption in datacenters is key to building low cost datacenters. To address this challenge, we explore the potential of hybrid datacenter designs that mix low power platforms with high performance ones. We show how these designs can handle diverse workloads with different service level agreements in an energy efficient fashion. We evaluate the feasibility of our approach through experiments and then discuss the design challenges and options of hybrid datacenters.

Performance Comparison of Graphene Nanoribbon FETs With Schottky Contacts and Doped Reservoirs

We propose that lateral heterostructures of single-atomic-layer graphene and hexagonal boron-carbon-nitrogen (hBCN) domains, can represent a powerful platform for the fabrication and the technological exploration of real two-dimensional field-effect transistors. Indeed, hBCN domains have an energy bandgap between 1 and 5 eV, and are lattice-matched with graphene; therefore they can be used in the channel of a FET to effectively inhibit charge transport when the transistor needs to be switched off. We show through ab initio and atomistic simulations that a FET with a graphene-hBCN-graphene heterostructure in the channel can exceed the requirements of the International Technology Roadmap for Semiconductors for logic transistors at the 10 and 7 nm technology nodes. Considering the main figures of merit for digital electronics, a FET with gate length of 7 nm at a supply voltage of 0.6 V exhibits I(on)/I(off) ratio larger than 10(4), intrinsic delay time of about 0.1 ps, and a power-delay-product close to 0.1 nJ/m. More complex graphene-hBCN heterostructures can allow the realization of different multifunctional devices, translating on a truly two-dimensional structure some of the device principles proposed during the first wave of nanoelectronics based on III-V heterostructures, as for example the resonant tunneling FET.

An energy case for hybrid datacenters

We explore the device potential of a tunable-gap bilayer graphene (BG) FET exploiting the possibility of opening a bandgap in BG by applying a vertical electric field via independent gate operation. We evaluate device behavior using atomistic simulations based on the self-consistent solution of the Poisson and Schrodinger equations within the nonequilibrium Greens function formalism. We show that the concept works, but the bandgap opening is not strong enough to suppress band-to-band tunneling in order to obtain a sufficiently large Ion/Ioff ratio for CMOS device operation.