Francesco Brianti

High-speed autozeroed CMOS comparator for multistep A/D conversion

Abstract A CMOS comparator suitable for multi-step flash analog-to-digital (A/D) converters is presented. It includes a moderate-gain preamplifier, a gain stage and a final set-reset-flip-flop. Fast operation and high resolution are achieved using regenerative loads in the gain stage together with reset and autozero techniques in both amplifying stages. To minimize residual offset, the regenerative structure is reset while still kept in its unstable configuration. The comparator was integrated in conventional single-poly 1.2 μm CMOS technology. Experimental evaluations showed a better than 1.5 mV resolution with less than 400 μV offset at a larger than 30 MHz comparison rate after the sampling/autozero phase. Power dissipation is as small as 0.8 mW (VDD = 5 V) in static conditions, and within 2.2 mW at maximum operating frequency.