Roberto Alini

A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo

A fully integrated partial response maximum likelihood (PRML) read/write IC with analog adaptive equalization operates up to 200 MSample/s. The chip implements both matched spectral null (MSN) trellis and standard PR4 Viterbi detectors in the digital domain as well as digital servo. The device is integrated in a mature 0.7-/spl mu/m BiCMOS technology, has a die size of 54 mm/sup 2/, and dissipates 2 W with MSN code or 1.5 W with PR4 code at 4.5-V supply and 200 MSample/s.

A 200 MSample/s trellis-coded PRML read/write channel with digital servo

A fully-integrated R/W IC operates at 200 MSample/s channel rate and supports two recording codes: a rate 4/5 (0,4/8) matched spectral null (MSN) trellis code and associated detector, and a rate 8/9 (0,4/4) with a standard maximum-likelihood PR4 detector. The chip supports a complete flexible digital servo and four-level write precompensation to overcome media nonlinearity. The device is integrated in 0.7 /spl mu/m BiCMOS technology, has 54 mm/sup 2/ die and uses 2 W with MSN code or 1.5 W with PR4 code at 4.5 V and 200 MSample/s. This chip avoids external interface chips, incorporating an ADC and functions useful to the servo DSP. MSN code provides approximately 2 dB gain in SNR with respect to rate 8/9 PR4 coding at a user density of PW/sub 50//T/sub max/=1.8.

A single-chip 9-32 mb/s read/write channel for disk-drive applications

This paper reports on a single-chip read/write channel for disk drive. The integrated circuit implements a peak detector architecture fully compatible with zoned-bit recording applications. The chip contains all the functions needed to implement a high performance read channel like pulse detector, programmable active filter, servo demodulator, frequency synthesizer and data separator. The design take fully advantage of the feature available in a BICMOS technology to achieve power saving, high speed and immunity to cross-talk from digital to analog. The IC is fabricated in a 1.2 ¿m BiCMOS technology and has an active area of approximately 28 mm2. While operating from a single 5 V supply the power consumption is only 450 mW at 32Mbit/s.

Novel linearization circuit for BiCMOS transconductors used in high frequency OTA-C filters

A novel linearization circuit for a tunable BiCMOS transconductor based on the emitter degeneration of bipolar devices is analyzed. The transconductor is suitable for high-frequency continuous-time filter implementations because of the large value of the gm/I ratio and its ease of tunability. An integrator cell with a unity gain bandwidth of up to 80 MHz can be realized with a capacitive load as large as 3 pF and a power consumption of about 3.5 mW. An extended tuning range can be achieved through the proposed linearization circuit that reduces the total harmonic distortion (THD) in the lower part of the tuning range. Simulation program with IC emphasis (SPICE) simulation results are presented, comparing the classical solution with respect to the linearized one; the input stage shows an output current THD less than 1% for an input differential signal of up to 500m V/sub pp/ over an almost 10:1 tuning range.<<ETX>>

High-speed BiCMOS operational amplifier for switched-capacitor circuits

A high-speed fully-differential operational amplifier (op-amp) realized in 2-/spl mu/ BiCMOS technology is proposed. Input MOS buffers allow the use of this op-amp in switched capacitor (SC) circuits with high clock frequency (up to 75 MHz). The gain stage is realized with resistively-loaded bipolar devices. No common mode feedback is required. This saves area and power and increases speed. The op-amp presents a DC gain of about 46 dB with a unity-gain frequency as large as 700 MHz with 1.5 pF load. The measured performance of closed-loop settling time (1%) is about 12 ns.<<ETX>>