Francesco Carrara

A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control

This paper presents the design and measured performance of a 1.8-GHz power amplifier featuring load mismatch protection and soft-slope power control. Load-mismatch-induced breakdown can be avoided by attenuating the RF power to the final stage during overvoltage conditions. This was accomplished by means of a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. The issue of output power control has been addressed as well. To this end, a temperature-compensated bias network is proposed, which allows a moderate power control slope (dB/V) to be achieved by varying the circuit quiescent current according to an exponential law. The nonlinear power amplifier was fabricated using a low-cost silicon bipolar process with a 6.4-V breakdown voltage. It delivers a 33.5-dBm saturated output power with 46% maximum power-added efficiency and 36-dB gain at a nominal 3.5-V supply voltage. The device is able to tolerate a 10:1 load standing-wave ratio up to a 5.1-V supply voltage. Power control slope is lower than 80 dB/V between -15 dBm and the saturated output power level.

A 90nm CMOS 5Mb/s crystal-less RF transceiver for RF-powered WSN nodes

In this work, a batteryless CMOS RF transceiver for WSN nodes is presented. It includes a fully functional receiver for symmetrical RX/TX throughput and exploits narrowband active transmission to improve the uplink reading range without burdening the reader complexity. A PLL-based architecture is adopted both to recover incoming data and synthesize the TX carrier from the input RF signal. This enables crystal-less operation, thus minimizing the system com- plexity and cost.

VSWR-protected silicon bipolar power amplifier with smooth power control slope

A 1.8 GHz silicon bipolar PA is presented. A protection circuit enables the amplifier to sustain a 10:1 load VSWR at 5 V supply despite a low BV/sub ceo/ of 6.5 V. A temperature-compensated bias network allows a moderate power-control slope of less than 80 dB/V. A 50% PAE is attained at a 33.8 dBm output power level. The 1.2/spl times/1.5 mm/sup 2/ die is implemented in 0.8 /spl mu/m BiPMOS.