Antonino Scuderi

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-¿m 2.5-V standard I/O FETs in a 0.13-¿m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control

A digitally modulated power amplifier (DPA) in 1.2 V 0.13 mum SOI CMOS is presented, to be used as a building block in multi-standard, multi-band polar transmitters. It performs direct amplitude modulation of an input RF carrier by digitally controlling an array of 127 unary-weighted and three binary-weighted elementary gain cells. The DPA is based on a novel two-stage topology, which allows seamless operation from 800 MHz through 2 GHz, with a full-power efficiency larger than 40% and a 25.2 dBm maximum envelope power. Adaptive digital predistortion is exploited for DPA linearization. The circuit is thus able to reconstruct 21.7 dBm WCDMA/EDGE signals at 1.9 GHz with 38% efficiency and a higher than 10 dB margin on all spectral specifications. As a result of the digital modulation technique, a higher than 20.1 % efficiency is guaranteed for WCDMA signals with a peak-to-average power ratio as high as 10.8 dB. Furthermore, a 15.3 dBm, 5 MHz WiMAX OFDM signal is successfully reconstructed with a 22% efficiency and 1.53% rms EVM. A high 10-bit nominal resolution enables a wide-range TX power control strategy to be implemented, which greatly minimizes the quiescent consumption down to 10 mW. A 16.4% CDMA average efficiency is thus obtained across a > 70 dB power control range, while complying with all the spectral specifications.

A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control

This paper presents the design and measured performance of a 1.8-GHz power amplifier featuring load mismatch protection and soft-slope power control. Load-mismatch-induced breakdown can be avoided by attenuating the RF power to the final stage during overvoltage conditions. This was accomplished by means of a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. The issue of output power control has been addressed as well. To this end, a temperature-compensated bias network is proposed, which allows a moderate power control slope (dB/V) to be achieved by varying the circuit quiescent current according to an exponential law. The nonlinear power amplifier was fabricated using a low-cost silicon bipolar process with a 6.4-V breakdown voltage. It delivers a 33.5-dBm saturated output power with 46% maximum power-added efficiency and 36-dB gain at a nominal 3.5-V supply voltage. The device is able to tolerate a 10:1 load standing-wave ratio up to a 5.1-V supply voltage. Power control slope is lower than 80 dB/V between -15 dBm and the saturated output power level.

Balanced SiGe PA Module for Multi-Band and Multi-Mode Cellular-Phone Applications

In this paper, the integration of a MM (GSM/EDGE/WCDMA) MB (850/900MHz, 1800/1900/2100MHz) 50 Omega-matched isolator-less flip-chip PAs, capable of envelope and power tracking operation, is discussed. The PAs are integrated in a 0.25 mum SiGe technology and are soldered on a 4-layer substrate. The system is hosted in a 6 x 8 mm2 plastic module.

Fully printed organic CMOS technology on plastic substrates for digital and analog applications

Drastic efforts have been realized these last years in order to develop complementary organic technology. This is the essential key to produce elementary low-cost circuits for digital and analog applications. Different techniques [1–3] are available nowadays to obtain both N- and/or P-type organic devices. Screen printing is one of the most highly awaited low-cost techniques that can be used to produce organic devices and circuits. It has been widely used in P-type organic technologies [4, 5]. Now that N-type semiconductors have become much more easily processed, developers are seeking a complete CMOS and lifetime robust technology. Many previous works have reported on a complete solution based on CMOS technology [6–8]. Large-area-compatible organic processes have also been demonstrated [9]. Nevertheless some of the technological steps in these latter reports are not fully printed and/or still present some lithography/vacuum deposition steps. We present here a complete fully printed CMOS technology on flexible substrates showing acceptable device performances and digital/analog circuit functionalities, which can lead to more complex designs.

A 4b ADC manufactured in a fully-printed organic complementary technology including resistors

Organic transistors (OTFTs) can be printed on thin plastic substrates to obtain mechanically flexible large-area electronics with high throughput. Examples of applications include sensor-augmented RFIDs fabricated on the packaging of retail items and smart surfaces integrating sensors or actuators. Printed OTFTs have been used to design circuits [1-4], however, these implementations have been mainly limited to digital circuits or large-area switch matrices. A major challenge in the design of printed circuits is the relatively high variability in the characteristics of the OTFTs, which is caused by the low degree of spatial correlation typical of printing processes. A relatively high rate of hard faults is also typical in printed electronics (at the state of the art, yield is acceptable only for a circuit complexity of ~100 transistors).

Design of a Wideband High-Voltage High-Efficiency BiCMOS Envelope Amplifier for Micro-Base-Station RF Power Amplifiers

A high-performance bipolar-CMOS-DMOS (BCD) monolithic envelope amplifier for micro-base-station power amplifiers (PAs) is presented. Measurement of the BCD high-voltage (VDD = 15 V) envelope amplifier shows an efficiency of 72% using 7.7-dB peak-to-average ratio WCDMA input signals at an average envelope amplifier output power above 3 W. A WCDMA envelope-tracking RF PA at 2.14 GHz, including a GaN field-effect transistor RF stage, has an overall drain efficiency above 51%, with a normalized power root-mean-square error below 1.2% and an adjacent channel leakage ratio of -49 dBc at 5-MHz offset using memory-effect mitigation digital pre-distortion, at an average output power above 2 W and a gain of 10 dB.

Degradation Mechanisms in CMOS Power Amplifiers Subject to Radio-Frequency Stress and Comparison to the DC Case

An in-depth study of the degradation dynamics in CMOS power amplifiers is presented. The transistor was operated at 1.9 GHz under real-world load and power conditions. Threshold voltage and sub-threshold slope were monitored as a measure of the device degradation versus stress time. Experimental evidence is provided, which demonstrates that damage severity strongly depends on the features of drain voltage and current waveforms, rather than on average dissipated power. The results of RF stress tests are compared to dc hot carrier and Fowler-Nordheim experiments. Large discrepancies are found between measurements and the quasi-static model.

A 33-dBm 1.9-GHz silicon-on-insulator CMOS stacked-FET power amplifier

A single-stage stacked-FET power amplifier (PA) is demonstrated using a 0.28-µm silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. The stacked-FET PA has been designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. The measurement results show that, with a 6.5-V supply, the PA achieves a small-signal gain of 13.2 dB, a saturated output power of 33 dBm, and a maximum power-added-efficiency (PAE) of 47% at 1.9 GHz. This is the first reported stacked-FET PA in submicron SOI CMOS technology that delivers multi-Watt output power in the GHz range. It also maintains high power efficiency over a wide range of supply voltages.

A high performance RF power amplifier with protection against load mismatches

A high performance power amplifier is presented which includes a protection circuitry against load impedance variations. Load mismatches produce peak voltages on the power transistor collector that give rise to breakdown conditions and hence to permanent faults. The protection circuitry is based on a feedback loop that acts on the amplifier gain to limit the overdrive of the output transistor. A monolithic power amplifier for 1.8-GHz DCS-PCS applications was integrated in a silicon bipolar technology with a 4.3-V breakdown voltage. The amplifier delivers a 33-dBm output power with 51% power-added efficiency and 33-dB gain at a nominal 3-V supply voltage. Standing wave ratio was tested up to 20:1 for all phases with a supply voltage up to 3.8 V without damage to the device.