Francesco Rossi

Low complexity LDPC code decoders for next generation standards

This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture

VLSI design of a high-throughput multi-rate decoder for structured LDPC codes

Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18/spl mu/m standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2dB down to BER=10/sup -8/), low latency (less than 6.0/spl mu/s), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).

Layered Decoding of Non-Layered LDPC Codes

The principle of layered decoding is extended to those codes not especially conceived for this practice, as to benefit of the increased convergence speed. Two different strategies are considered to solve the problem and the related architectures presented: one more straightforward, and based on the use for the soft output of the last value originated in a layer; the other based on the computation of the variation (or delta) of the soft output metrics to allow concurrent updates. Then, as in architecture-first approach, the performance is assessed for several widths of the layer, which remarks the robustness of the delta-mechanism to high parallelisation factors. As in the exact layered decoding, the average boost of two times in the convergence speed is shown

A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes

This paper describes a scalable IP of a decoder for LDPC codes compliant to IEEE 802.1 In and running the well- known layered decoding algorithm. The decoder architecture is arranged in clusters of serial processing units, which are configurable to process all the codes in the standard and, at the same time, to support multiple frame decoding. An optimization methodology of the iteration latency is also described, which relates to the order of the messages updated by the processors, as well as to the sequence of layers the decoder goes through. The logic synthesis on 65 nm CMOS technology with low- power standard-cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 180 to 410 Mbps, and the power consumption being below 235 mW.

A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes

This paper describes a scalable architecture of a decoder for IEEE 802.11n low-density parity-check (LDPC) codes. The decoder runs the layered decoding algorithm and its architecture is arranged in clusters of serial functional units, which are configured to process all codes in the standard. The decoder works in pipeline, and a very effective technique to re- arrange the sequence of its elaborations is proposed in order to minimize the iteration latency; this relates to the order of the messages input and output by the processing units, as well as the sequence of layers followed for decoding. Moreover, memory optimization techniques have been applied to get a very efficient partitioning, allowing the pipeline of the operations. The synthesis on 65 nm CMOS technology with low-power standard- cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 136 to 355 Mbps, and the power consumption being below 185 mW.

High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes

As an enhancement of the state-of-the-art solutions, a high-throughput architecture of a decoder for structured LDPC codes is presented in this paper. Thanks to the peculiar code definition and to the envisaged architecture featuring memory paging, the decoder is very flexible, and the support of different code rates is achieved with no significant hardware overhead. A top-down design flow of a real decoder is reported, starting from the analysis of the system performance in finite-precision arithmetic, up to the VLSI implementation details of the elementary modules. The synthesis of the whole decoder on 0.18 μm standard cells CMOS technology showed remarkable performances: small implementation loss (0.2 dB down to BER = 10-8), low latency (less than 6.0 μs), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).

Techniques and architectures for hazard-free semi-parallel decoding of LDPC codes

The layered decoding algorithm has recently been proposed as an efficient means for the decoding of low-density parity-check (LDPC) codes, thanks to the remarkable improvement in the convergence speed (2x) of the decoding process. However, pipelined semi-parallel decoders suffer from violations or hazards between consecutive updates, which not only violate the layered principle but also enforce the loops in the code, thus spoiling the error correction performance. This paper describes three different techniques to properly reschedule the decoding updates, based on the careful insertion of idle cycles, to prevent the hazards of the pipeline mechanism. Also, different semi-parallel architectures of a layered LDPC decoder suitable for use with such techniques are analyzed. Then, taking the LDPC codes for the wireless local area network (IEEE 802.11n) as a case study, a detailed analysis of the performance attained with the proposed techniques and architectures is reported, and results of the logic synthesis on a 65u2009nm low-power CMOS technology are shown.

Design and Validation of Digital Channels for a Galileo Receiver Prototype

This paper describes the design activity for the digital baseband processing of a prototype receiver for the Galileo system. According to the applied hardware-software partitioning, the high rate elaborations have been implemented on a dedicated hardware, a Xilinx Virtex2 FPGA, while the remaining low rate processing has been programmed on an analog device DSP. A customarily designed prototype board has been used to validate the receiver under real working conditions: a dynamic GPS and Galileo scenario. Particularly, the paper focuses on the receiver digital channel, which is the critical core of the FPGA, from VHDL modeling to hardware implementation and testing

Reply to "Comments on Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes"

This is a reply to the comments by Gunnam et al. Comments on Techniques and architectures for hazard-free semi-parallel decoding of LDPC codes, EURASIP Journal on Embedded Systems, vol. 2009, Article ID 704174 on our recent work Techniques and architectures for hazard-free semi-parallel decoding of LDPC codes, EURASIP Journal on Embedded Systems, vol. 2009, Article ID 723465.