Massimo Rovini

Low complexity LDPC code decoders for next generation standards

This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture

VLSI design of a high-throughput multi-rate decoder for structured LDPC codes

Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18/spl mu/m standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2dB down to BER=10/sup -8/), low latency (less than 6.0/spl mu/s), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).

A multi-standard flexible turbo/LDPC decoder via ASIC design

This paper describes the first complete design of a single-core multi-standard flexible Turbo/LDPC decoder using an ASIC approach. Such a solution outperforms other state-of-the-art implementations based on application-specific instruction-set processors (ASIPs), which are shown to suffer from impaired throughput and power consumption. In this paper, we describe in detail the VLSI flexible architecture of a decoder coping with all the modern communication standards defining LDPC and Turbo codes, and provide a proof-of-concept implementation complaint with 3GPP-HSDPA, DVB-SH, IEEE 802.16e and IEEE 802.11n standards. The decoder, running at only 150MHz for a reduced power, occupies an area of 0.9mm2 with a maximum power consumption of only 86.1mW.

A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes

This paper describes a scalable IP of a decoder for LDPC codes compliant to IEEE 802.1 In and running the well- known layered decoding algorithm. The decoder architecture is arranged in clusters of serial processing units, which are configurable to process all the codes in the standard and, at the same time, to support multiple frame decoding. An optimization methodology of the iteration latency is also described, which relates to the order of the messages updated by the processors, as well as to the sequence of layers the decoder goes through. The logic synthesis on 65 nm CMOS technology with low- power standard-cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 180 to 410 Mbps, and the power consumption being below 235 mW.

Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes

Low-density parity-check (LDPC) codes have recently been included as error-correcting codes in IEEE 802.16e, for wireless metropolitan area networks. This paper proposes a flexible, low-complexity LDPC decoder fully compliant with all 114 codes defined by the standard. The decoder runs the layered decoding algorithm to increase the convergence speed, and relies on a semi-parallel implementation with serial processing units working in pipeline to reduce the latency. Particularly, two different architectures are considered, and their RTL/memory complexity tradeoffs are analyzed. The resulting design yields a throughput ranging from 93 to 497 Mbps by means of 15 iterations at the clock frequency of 400 MHz. Synthesis on 65 nm CMOS technology, shows a chip area less than 0.59 mm2, despite the high flexibility, which compares favourably with similar implementations.

A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes

This paper describes a scalable architecture of a decoder for IEEE 802.11n low-density parity-check (LDPC) codes. The decoder runs the layered decoding algorithm and its architecture is arranged in clusters of serial functional units, which are configured to process all codes in the standard. The decoder works in pipeline, and a very effective technique to re- arrange the sequence of its elaborations is proposed in order to minimize the iteration latency; this relates to the order of the messages input and output by the processing units, as well as the sequence of layers followed for decoding. Moreover, memory optimization techniques have been applied to get a very efficient partitioning, allowing the pipeline of the operations. The synthesis on 65 nm CMOS technology with low-power standard- cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 136 to 355 Mbps, and the power consumption being below 185 mW.

High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes

As an enhancement of the state-of-the-art solutions, a high-throughput architecture of a decoder for structured LDPC codes is presented in this paper. Thanks to the peculiar code definition and to the envisaged architecture featuring memory paging, the decoder is very flexible, and the support of different code rates is achieved with no significant hardware overhead. A top-down design flow of a real decoder is reported, starting from the analysis of the system performance in finite-precision arithmetic, up to the VLSI implementation details of the elementary modules. The synthesis of the whole decoder on 0.18 μm standard cells CMOS technology showed remarkable performances: small implementation loss (0.2 dB down to BER = 10-8), low latency (less than 6.0 μs), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).

A flexible state-metric recursion unit for a multi-standard BCJR decoder

This paper describes the architecture of a flexible and reconfigurable processor for the computation of the state-metric recursion in a multi-standard BCJR decoder. The unit can serve binary as well as duo-binary codes with any number of states. The architecture is arranged into a cluster of state-metric processors plus two multiplexing networks for feedback and normalization, configured on-the-fly for the code in use. An optimized solution is presented allowing the support of every code among 8-state duo-binary, 8-state binary and 2-state binary codes, i.e., of every Turbo and LDPC code defined by the modern communication standards. The logical synthesis on different CMOS technologies shows that the architecture attains a maximum clock frequency of 450 MHz. Finally, the complexity overhead of such a flexible design is only about 18% w.r.t. optimized single-standard solutions.

Fixed-point MAP decoding of channel codes

This paper describes the fixed-point model of the maximum a posteriori (MAP) decoding algorithm of turbo and low-density parity-check (LDPC) codes, the most advanced channel codes adopted by modern communication systems for forward error correction (FEC). Fixed-point models of the decoding algorithms are developed in a unified framework based on the use of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. This approach aims at bridging the gap toward the design of a universal, multistandard decoder of channel codes, capable of supporting the two classes of codes and having reduced requirements in terms of silicon area and power consumption and so suitable to mobile applications. The developed models allow the identification of key parameters such as dynamic range and number of bits, whose impact on the error correction performance of the algorithm is of pivotal importance for the definition of the architectural tradeoffs between complexity and performance. This is done by taking the turbo and LDPC codes of two recent communication standards such as WiMAX and 3GPP-LTE as a reference benchmark for a mobile scenario and by analyzing their performance over additive white Gaussian noise (AWGN) channel for different values of the fixed-point parameters.

Implementation of message-passing algorithms for the acquisition of spreading codes

A new technique to acquire pseudo-noise (PN) sequences has been recently proposed in [1] and [2]. It is based on the paradigm of iterative message passing (iMP) to be run on loopy graph. This technique approximates the maximum-likelihood (ML) estimator, providing a sub-optimal algorithm that searches all possible code phases in parallel, at low complexity and fast acquisition time. This work is addressed to the design of the architecture of an iMP detector, following the implementation methodologies typical of standard low-density parity-check (LDPC) decoders, and demonstrates its benefits in terms of acquisition time and complexity, compared with standard techniques.