Nicola E. L'Insalata

Low complexity LDPC code decoders for next generation standards

This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture

Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

Clock distribution is an important issue when designing multi processor systems-on-chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a multi processor tiled architecture based on a network-on-chip communication backbone on a CMOS 65 nm technology.

VLSI design of a high-throughput multi-rate decoder for structured LDPC codes

Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18/spl mu/m standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2dB down to BER=10/sup -8/), low latency (less than 6.0/spl mu/s), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).

Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems

This work presents an FFT/IFFT core compiler particularly suited for the VLSI implementation of OFDM communication systems. The tool employs an architecture template based on the pipelined cascade principle. The generated cores support run-time programmable length and transform type selection, enabling seamless integration into multiple mode and multiple standard terminals. A distinctive feature of the tool is its accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results of the generated macrocells are presented for two deep sub-micron standard-cells libraries (65 and 90nm) and commercially available FPGA devices. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity expressed as gate count and RAM/ROM bits, while keeping the same system level performance in terms of throughput, transform size and numerical accuracy.

High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes

As an enhancement of the state-of-the-art solutions, a high-throughput architecture of a decoder for structured LDPC codes is presented in this paper. Thanks to the peculiar code definition and to the envisaged architecture featuring memory paging, the decoder is very flexible, and the support of different code rates is achieved with no significant hardware overhead. A top-down design flow of a real decoder is reported, starting from the analysis of the system performance in finite-precision arithmetic, up to the VLSI implementation details of the elementary modules. The synthesis of the whole decoder on 0.18 μm standard cells CMOS technology showed remarkable performances: small implementation loss (0.2 dB down to BER = 10-8), low latency (less than 6.0 μs), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).

Low-complexity FFT/IFFT IP hardware macrocells for OFDM and MIMO-OFDM CMOS transceivers

The paper presents an automated environment for fast design space exploration and automatic generation of FFT/IFFT macrocells with minimum circuit and memory complexity within the numerical accuracy budget of the target application. The effectiveness of the tool is demonstrated through FPGA and CMOS implementations (90nm, 65nm and 45nm technologies) of the baseband processing in embedded OFDM transceivers. Compared with state-of-art FFT/IFFT IP cores, the proposed work provides macrocells with lower circuit complexity while keeping the same system performance (throughput, transform size and accuracy) and is the first addressing the requirements of all OFDM standards including MIMO systems: 802.11 WLAN, 802.16 WMAN, Digital Audio and Video Broadcasting in terrestrial, handheld and hybrid satellite-scenarios, Ultra Wide Band, Broadband on Power Lines, xDSL.

Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems

This paper presents an environment for the automatic generation of FFT/IFFT cores. The cores are derived from a pipelined cascade architecture template supporting run-time programmable length, transform type selection and three different machine arithmetics (fixed-point, block floating-point and convergent block floating-point). The tool profiles arithmetics and generate the macrocell with the minimum operands bit-width (hence minimum circuit complexity) within the numerical accuracy budget given by the target application. Four case studies illustrate the use of the environment in multi-band OFDM communication systems (WLAN, xDSL, DVB-T/H and UWB). Implementation results of the generated macrocells are evaluated on a 65 nm CMOS standard cells library. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity (gate count, RAM/ROM bits) while keeping the same system level performance (throughput, transform size and numerical accuracy).

A mesochronous physical link architecture for network-on-chip interconnects

Clock distribution is a major issue when implementing system-on-a-chip in deep sub-micron technologies. This work presents a new mesochronous physical link architecture, named SKIL, which enables full bandwidth communication between macrocells clocked by signals with the same frequency and an arbitrary amount of skew. SKIL is implemented using standard-cells design flows. It introduces two clock cycles of latency and negligible area and leakage power overheads. Implementation results are presented on a 65 nm CMOS technology.

Analysis of FPGA Solutions for Baseband Processing in Multi Carrier Communication Standards for Consumer Applications

The paper presents FPGA-based reconfigurable implementations of the OFDM processing core for several communications standards of high interest for consumer devices. The proposed solutions are analyzed in terms of cost, power consumption and flexibility and compared with state-of-the-art implementations in semi-custom CMOS technology and FPGA.