Andrea Ghilioni

A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves

Wireless on-chip processing at millimeter waves still lacks key functions: quadrature generation enabling direct conversion architectures and simplifying phased-array systems, frequency division with an operating range wide enough to compensate spreads due to component variations. This paper addresses the implementation of these functions, introducing new circuit solutions. The quadrature voltage-controlled oscillator (VCO) relies on a ring of two tuned VCOs, where the oscillation frequency depends on inter-stage passive components only, demonstrating low noise and accurate quadrature phases. Prototypes, realized in 65-nm CMOS, show 56-60.4-GHz tunable oscillation frequency, phase noise better than 95 dBc/Hz at 1-MHz offset in the tuning range, 1.5 maximum phase error while consuming 22 mA from a 1-V supply. The frequency divider is based on clocked differential amplifiers, working as dynamic CML latches, achieving high speed and low power simultaneously. A divider by 4 realized in 65-nm CMOS occupies 15 m 30 m, features an operating frequency programmable from 20 to 70 GHz in nine bands and consumes 6.5 mW.

A mm-Wave quadrature VCO based on magnetically coupled resonators

Wireless signal processing at mm-Waves would benefit from the availability of a quadrature signal reference, enabling direct-conversion transceiver architectures and providing phase rotators drivers in phased arrays systems [1]. They are furthermore attractive for clock recovery in ICs for wireline applications. Search of a compact quadrature generator at around 60GHz with low phase noise at moderate power is the topic of this work. Discarding a double-frequency VCO followed by dividers-by-two given the high frequency range of operation, the most suitable topology borrowed by RF solutions is represented by cross-coupled LC voltage-controlled oscillators [2]. However, the oscillation frequency dependence on the biasing current makes it susceptible to phase noise, close-in in particular [3]. At mm-Waves, this is exacerbated by core devices of small dimensions to such an extent that 1/f3 noise remains dominant up to more than ∼10MHz, making it unsuitable for stringent applications. On the contrary a ring of two VCOs magnetically coupled to each other, as shown in Fig. 16.2.1, has an oscillation frequency dependence on inter-stage passive components only, low 1/f3 noise together with good quadrature accuracy. The quadrature oscillator has been realized in a 65nm CMOS technology and prototypes show the following performances: 56-to-60.3GHz tunable oscillation frequency, phase noise better than −95dBc/Hz at 1MHz offset in the tuning range, 1.5° maximum phase error while consuming 22mA from a 1V supply.

A 40–67 GHz Power Amplifier With 13 dBm

Pushed by the availability of large fractional bandwidths, many well-established applications are focusing mm-wave spectrum for product deployment. Generation of broadband power at mm-waves is challenging because a key target such as the efficiency trades with the gain-bandwidth (GBW) product. The major limit is the capacitive parasitics at the interstage between driver and power devices. The latter are designed with a large form factor so as to deliver the desired output power and are commonly biased in class-AB to achieve high drain efficiency, penalizing GBW. In this paper, a design methodology for interstage and output matching networks targeting large fractional bandwidth and high efficiency is proposed. Leveraging inductively coupled resonators, we apply Norton transformations for impedance scaling. In both networks, topological transformations are employed to include a transformer, achieve the desired load impedance and minimize the number of components. A two-stage differential PA with neutralized common source stages has been realized in 28 nm CMOS using low-power devices. The PA delivers 13 dBm saturated output power over the 40-67 GHz bandwidth with a peak power-added efficiency of 16% without power combining. To the best of authors knowledge, the presented PA shows state-of-the-art performances with the largest fractional bandwidth among bulk CMOS mm-wave PAs reported so far.

{\rm P}_{\rm SAT}

The availability of wide-band low-power frequency dividers is fundamental in transceivers for emerging mm-wave applications. Up to date injection locked topologies have been investigated for very high frequency operations but at the price of large area and limited frequency range. In this work, we investigate a new class based on dynamic latches with load modulation. The proposed latches can be viewed as the evolution of classic static CML latches where the regenerative cross-coupled pair is removed for minimum parasitic at output nodes, i.e., maximum speed, and loads are modulated by the input clock for maximum charge retention during hold times. A time-domain circuit inspection aimed at deriving analytical expressions for maximum and minimum operation frequency and providing guidelines for optimum design is reported. Prototypes of dividers by 4, realized in 32 nm bulk CMOS, operate between 14 GHz and 70 GHz, demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8 mW of maximum power consumption and 55 ×18 μm2 occupied area.

and 16% PAE in 28 nm CMOS LP

With a cut-off frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding from Radio Frequency to mm-Waves applications. Frequency dividers are key building blocks for LO generation in wireless transceivers and clock synchronization in front-ends for wire-line and optical communications. Dividers based on traditional static CML latches work over a wide band but power dissipation at mm-Waves is extremely large. To save power, recently reported mm-Wave PLLs propose tunable narrowband dividers, based on injection-locking techniques, together with digital calibration algorithms [1,2]. On the other hand, for division factors higher than 2, the frequency locking range of injection-locked oscillators is very limited, mandating fine and frequent calibrations. This paper introduces clocked differential amplifiers, working as dynamic CML latches, to realize high speed and low power mm-Wave dividers. The solution is very compact, which is particularly desirable at mm-Waves to ease chip layout and shorten IC interconnections, minimizing signal losses. A frequency divider-by-4 has been realized in a 65nm bulk CMOS technology and prototypes prove an operating frequency programmable from 20 to 70GHz. The frequency range in each sub-band spans from 10% to 17%, corresponding to a 2.5x to 4x improvement compared to injection-locked dividers-by-4. Maximum power dissipation is 6.5mW and occupied area is only 15μm × 30μm.

Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation

Silicon photonics platforms are emerging as attractive solutions for low power and cost effective short/medium-reach optical interconnects. To overcome the intrinsic limitations of monolithically integrated photonics with electronics, STMicroelectronics has developed a 3D-compatible silicon photonics platform that implements in the FEOL only optical devices. Photonics Integrated Circuits are made compatible with 3D assembly of Electronic Integrated Circuits through the use of copper pillars. In this paper we present a 25Gbps Opto-Electronic receiver operating at 1310nm wavelength, consisting of an integrated waveguide Germanium photodiode interfaced by means of copper pillars to a 65nm CMOS amplification chain. The receiver demonstrates an Average Optical Power sensitivity at photodiode input, at a BER of 10-12, of -11.9dBm with a PRBS7 input signal, corresponding to a 97μApp TIA input current. The achieved sensitivity is ~6dB better than state-of-the-art monolithically integrated silicon photonics receivers, at comparable TIA and LA power consumption.

A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz

In this scenario, this work presents a complete 25Gb/s silicon photonics electro-optical transmitter front-end comprising an MZM, using carrier depletion P-N junctions and operating at 1310nm wavelength, and a power-efficient CMOS driver. The transmitter optical path is integrated on STMicroelectronics 3Dcompatible silicon-photonics platform (PIC25G), which implements only optical devices in the front-end of line (FEOL) [4]. The electronic IC, realized in 65nm bulk CMOS technology, is 3D-assembled on top of the photonic IC by means of 20μm-diameter copper pillars, minimizing the interconnection parasitic capacitance. This 1310nm 25Gb/s silicon photonics electro-optical transmitter reports error-free operation with wide open optical eye diagrams at a competitive dynamic extinction ratio (ER) of up to 6dB using a depletion-mode MZM.

A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies

Mach-Zehnder-based modulator architectures lend themselves to the realization of high-data-rate Silicon Photonics transmitters. In this work the challenges set by the integration of such devices on silicon are analyzed in depth. The two main alternative electronic driver architectures, namely multistage and travelling wave, are compared with focus to power efficiency. This is, in fact, a key parameter when considering the stringent requirements of standard module form factors. A 25 Gbps multistage and a 56 Gbps travelling wave modulator have been realized. Each electro-optical transmitter is obtained by the 3D assembly of an electronic IC on top of a photonic IC through copper pillars. STMicroelectronics PIC25G Silicon Photonics platform has been adopted for the fabrication of optical devices, while 65 nm CMOS and 55 nm BiCMOS technologies are exploited to realize the electronic drivers. A 30% better power efficiency compared to Silicon Photonics state-of-the-art at similar data rates and comparable extinction ratio performance has been demonstrated in both cases. Since packaging is also a crucial aspect for Silicon Photonics high volume production, experiments on bare dice as well as on packaged chips are reported.

22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s

The ever-increasing data center IP traffic, up to 8.6 zettabytes per year by 2018 with nearly 3× growth since 2013 [1], requires power-efficient high-speed interconnects. Next generation optical interfaces will adopt 50Gbaud signaling [2], and minimizing power consumption is key to enable the use of small form-factor optical modules for electro-optical conversion. In this perspective, silicon photonics is an attractive alternative to discrete photonics, lending itself to higher miniaturization at reduced cost [3]. Furthermore, silicon photonics enables co-design of electronics with photonics, thus optimizing transceiver power efficiency. In particular, the electro-optical transmitter constitutes the main source of power consumption. Travelling wave Mach-Zehnder modulator (MZM) architectures are used in discrete photonics realizations as data rate increases, and lend themselves to silicon photonics. However silicon photonics suffers from electrical propagation losses and bandwidth limitations of integrated transmission lines, requiring equalization in the electronic driver to address 50Gbaud operation at moderate consumption and also in advanced node technologies. In this work, we employ a bifilar transmission line determining an electrical propagation loss of ~3dB/mm at 28GHz. Using an equalizer counteracts its effect, applying passive boost and shunt peaking in the pre-driving stage, combined with passive peaking in the load coupling. A 75% increase in the vertical aperture of the optical eye diagram is thus achieved with no power consumption penalty due to the equalizer. The complete electro-optical transmitter, operating at 56Gb/s at 1310nm wavelength, dissipates 300mW and ensures an extinction ratio (ER) higher than 2.5dB. This 56Gb/s silicon photonics transmitter displayes more than 30% power savings with respect to the state-of-the-art [4].

Insights Into Silicon Photonics Mach–Zehnder-Based Optical Transmitter Architectures

Frequency synthesizers at mm-waves would benefit from wide-band low-power dividers with large division factors. This work proposes a divider-by-4 based on clocked differential amplifiers working as dynamic CML latches. The clock modulates both the tail current and the load resistance of the differential pair, allowing a wide locking range. Prototypes, realized in 32nm CMOS, operate between 14GHz and 70GHz demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8mW of maximum power consumption and 55×18μm2 occupied area.