Francis Calmon

Time-Dependent Many-Particle Simulation for Resonant Tunneling Diodes: Interpretation of an Analytical Small-Signal Equivalent Circuit

A full many-particle (beyond the mean-field approximation) electron quantum-transport simulator, which is named BITLLES, is used to analyze the transient current response of resonant tunneling diodes (RTDs). The simulations have been used to test an analytical (free-fitting parameters) small-signal equivalent circuit for RTDs under stable direct-current-biased conditions. The comparison provides an excellent agreement and furnishes a way to physically interpret each circuit element. In addition, a nonlinear novel RTD behavior in the negative differential conductance region has been established, i.e. asymmetric time constants in the RTD current response when high-low or low-high voltage steps are considered.

A Simple Way for Substrate Noise Modeling in Mixed-Signal ICs

Here is a complete methodology of substrate noise modeling. The aim of this study is to predict the perturbations induced by digital commutations flowing through the substrate to reach sensitive analog blocks. Till now, the studies have only taking into account the parasitic elements of the bonding wires. This work consists of each part of a mixed-signal design that induces power-and-ground bounces: the printed circuit board, the package, the bonding wires, the input-output ring, the on-chip power-supply distribution, and the digital core of the chip. A standard approach, called integrated circuit (IC) emission model, is used to create the substrate simulation model. By adding some elements to this power-supply model, we can simulate the transient substrate voltage induced by the digital part of a mixed-signal IC. A test chip has been realized in a 0.35-mum BiCMOS process to validate this substrate coupling model. Power-supply network, chip activity and substrate propagation of this circuit are obtained by using classical computer-aided design tools. Some Spice simulations of the modeled test chip, running in many different configurations, are shown. Comparisons between measurements and simulations are done and lead to the conception of an optimized version of the same circuit that induces less parasitic substrate voltages

Tunnel Junction Engineering for Optimized Metallic Single-Electron Transistor

The development of metallic single-electron transistor (SET) depends on the downscaling and the electrical properties of its tunnel junctions (TJs). These TJs should insure high-ON current, low-OFF current, and low capacitance. We propose an engineered TJ based on multidielectric stacking. A number of high-k and low-k materials were considered to optimize the TJs characteristics. The optimized TJ is proven to increase the ION current and the ION/IOFF ratio in a double-gate SET. Using TiO2 plasma oxidation and Al2O3 atomic layer deposition, an SET proof of concept, with a double layer TJ, was fabricated and characterized.

Highly transparent low capacitance plasma enhanced atomic layer deposition Al2O3-HfO2 tunnel junction engineering

The development of metallic single electron transistor (SET) depends on the downscaling and the electrical properties of its tunnel junctions. These tunnel junctions should insure high tunnel current levels, low thermionic current, and low capacitance. The authors use atomic layer deposition to fabricate Al2O3 and HfO2 thin layers. Tunnel barrier engineering allows the achievement of low capacitance Al2O3 and HfO2 tunnel junctions using optimized annealing and plasma exposure conditions. Different stacks were designed and fabricated to increase the transparency of the tunnel junction while minimizing thermionic current. This tunnel junction is meant to be integrated in SET to enhance its electrical properties (e.g., operating temperature, I ON/I OFF ratio).

3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies

This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly will be successfully assessed, concretising the realism of a 3D technology for nomadic imaging systems.

Modelling of through silicon via and devices electromagnetic coupling

This paper is essentially composed of two parts for future synthesis. We developed 2D and 3D simulations, starting from a 0.35µm standard CMOS technology, focusing on through silicon via or redistribution layer induced coupling; nMOSFET, pMOSFET, and the sensitive regions of the CMOS inverter are investigated. We also study stacked devices in 3D circuits, in the radiofrequency range, and propagation of electromagnetic waves along some interconnections with discontinuities. This study is performed in the time domain-a finite-difference time-domain method is applied to the analysis of some vias flanked by two striplines, all embedded in silicon. Electric and magnetic field distributions, transmission and reflexion parameters, and pulse propagations along a transverse via are presented.

Single Electron Transistor analytical model for hybrid circuit design

A novel analytical and compact model of Single Electron Transistor (SET) is developed and implemented in Verilog-A language for use in hybrid SET-CMOS logic circuit design. The model is based on the steady state Master-Equation (ME). The implementation of this original and simple model, taking into account physical characteristics of tunnel junctions and the thermionic emission, has faithfully reproduced the behavior of metallic SET operating at room temperature. The hybrid SET-CMOS universal logic gate cell is analyzed to illustrate the efficiency of this compact SET model.

Single electron CMOS-like one bit full adder

This paper presents a comparative study of a one-bit-full-adder cell based on metallic complementary capacitively coupled single-electron transistors with its 22 nm CMOS counterpart. Performance and energy efficiency are investigated. The CMOS-like single-electron transistor based full adder is used in two operating mode, hysteresis and non-hysteresis. Parallel and serial single electron transistors designs are introduced. The single electron inverter consumes less than 90.4 pW while it dissipates 4.21 nW in CMOS technology.

Room temperature double gate single electron transistor based standard cell library

Single Electron Transistors have the potential to be a very promising candidate for future computing architectures due to their low voltage operation and low power consumption. In this paper, we present a family of digital logic cells based on double gate metallic SET working at room temperature. An evaluation of the performances characteristics in terms of power consumption and delay is detailed.

On the use of nanoelectronic logic cells based on metallic Single Electron Transistors

Single Electron Transistors have the potential to be a very promising candidate for future computing architectures due to their low voltage operation and low power consumption. In this paper, for the first time, logic cells based on metallic SET operating at room temperature and up to 125 °C were designed. An evaluation of the energy consumption and a comparison with their equivalents in CMOS technology has been made. Based on results using accurate SET model, SET-based logic cells provide a significant consumption reduction as compared with their CMOS counterparts.