Liviu Militaru

Study of the physical and electrical degradation of thin oxide films by atomic force microscope

The hillocks created by the application of ramped voltage stress on thin oxide films have been imaged using different modes of the atomic force microscope (AFM) and using conductive or insulating tips, leading to the conclusion that these anomalous hillocks correspond to real (physical) modification of the oxide’s surface. Electric force microscopy has also been used, which shows that negative charges are trapped in the oxide layer after the ramps and contribute to the contrast of AFM images although their role may not be predominant. Comparisons between ramps operated in air and in dry atmosphere or vacuum emphasize the role of the water layer covering the sample in the apparition of the hillock. The authors’ results tend to accredit that the formation of the hillock is a complex phenomenon involving a chemical (oxidation), electrical (trapped charges), and physical (electrothermal effect) mechanisms.

Study of Gate Oxide/Channel Interface Properties of SON MOSFETs by Random Telegraph Signal and Low Frequency Noise

The aim of this paper is the investigation of the gate stack properties of submicron MOSFETs integrated in silicon on nothing technology and the identification of traps responsible for the current fluctuations by random telegraph signal (RTS) technique and low frequency technique. We show that the analysis of devices having random discrete fluctuations in the drain current, the analysis of the RTS noise parameters (amplitude, high and low state durations, activation energy, capture cross section) as a function of bias voltage and temperature, allows us to characterize the traps located in the interface (HfO2-SiO2)/Si. The conventional technique consists of statistical treatment of the RTS time-domain data. The study of RTS noise in submicron SON MOS transistors offers the opportunity of studying the trapping/detrapping behavior of a single interface trap. Furthermore, it has convincingly been shown that this discrete switching of the drain current between a high and a low state is the basic feature responsible for l/fγ flicker noise in MOSFETs transistors.

Investigation of deep traps in silicon–germanium epitaxial base bipolar transistors with a single polysilicon quasi self-aligned architecture

The electrical properties of Si/Si1−xGex bipolar transistors have been analysed at temperatures ranging from 77 to 500 K. The investigated SiGe base transistors were fabricated using a BiCMOS single-polysilicon quasi self-aligned process, where base implant had been replaced by selective epitaxy on the base active area. At low temperature, static current–voltage measurements show a degradation of base current ideality, whereas collector current remains ideal over the whole temperature range. By studying forward and reverse currents at emitter–base and base–collector junctions, we have established that deep levels were involved in conduction phenomena at these junctions. Detailed measurements using capacitance transient spectroscopy (with different reverse and filling pulse voltages and different filling pulse durations) have revealed the presence of two deep levels along the periphery of the emitter. These deep levels have been found with identical characteristics at both junctions. It is demonstrated that these traps are most probably induced by the extrinsic base implantation.

Study of trap centres in silicon nanocrystal memories

Abstract This work reports on a comprehensive study of trapping centres in Si nanocrystal based memories. Silicon nanotrap memories have been studied using static, transient and low frequency techniques in the 80–400 K temperature range. Fast traps at the SiO 2 /substrate interface have been characterised by I – V – T and charge pumping (CP) techniques and we have shown that the density of fast traps drastically increases below 150 K from a few 10 10 cm −2 eV −1 up to a few 10 11 cm −2 eV −1 . DLTS experiments have shown that the fast interfacial traps are mainly located at Ec −0.26 eV with a capture cross section of 2.1×10 −15 cm 2 . The spectroscopic study of nc-Si has been performed on thin tunnel oxides from 0.8 to 2.0 nm. We have been able to discriminate slow traps and fast traps with temperatures above 300 K with the CP technique which allows measurements from 10 Hz to 1 MHz. Using DLTS, we have been able to observe tunnel emission from nc-Si around 250 K for emission rate windows of 2.3 and 4.6 Hz. At room temperature, we show that the stored electrons in the memory are not only located on the nanocrystals. The interface traps between the deposited high temperature oxide (HTO) and the thermal oxide are shown to play a significant role. The trapping mechanisms on nc-Si seems to be related both to the nc-Si surface at low T and to the quantum levels at high T . We have shown that above 350 K, most of the trapping mechanisms are due to the Si quantum dots.

Coulomb-blockade in nanometric Si-film silicon-on-nothing (SON) MOSFETs

The advantages of using architectures with gate nonoverlapped with source/drain have already been demonstrated in order to measure controlled single electron effects in planar MOSFETs. In this paper, we performed nonoverlapped silicon-on-nothing (SON) transistors with Si-film from 15 down to 9 nm. This leads to the fabrication of a quantum box (QB) defined by two lateral potential barriers in a thin Si-film (due to the camels back shape of the potential along the channel), and by two vertical potential barriers due to the gate oxide and to the buried dielectric of the SON architecture. This small volume device behaves like a quantum box, and we demonstrated that its own capacitance and consequently the Coulomb-blockade properties were mainly determined by the conduction film thickness. As the SON technology allows us to perform higly-performant fully depleted devices from bulk substrate, we will see in this paper that such devices can easily be adapted in order to fabricate three-dimensional QB, which becomes an alternative to fabricate SET with standard CMOS process.

RTS noise in submicron SiGe epitaxial base bipolar transistors

Abstract In this paper, we report a comprehensive study of Random Telegraph Signal (RTS) noise in SiGe epitaxial base bipolar transistors. We analyse the multilevel fluctuations of base and emitter forward currents before and after reverse stress on the emitter-base junction. We show the influence of the chemical treatment preceeding polysilicon emitter deposition on noise properties. We identified that RTS noise arises from different regions in the device : the silicon/polysilicon interface if an oxidizing surface preparation is used, and the emitter periphery after stress-induced degradation. Temperature and bias dependent measurements allowed us to characterize these defects (activation energy, defect type), to analyse their impact to the low frequency noise properties of these transistors and to discuss the role of hot carrier stressing.

Time domain and frequency analysis of RTS noise in deep submicron SiGe HBTs

Abstract Our work is focused on the identification of defects responsible for the current fluctuations at the origin of low-frequency noise or random telegraphic signals in industrial 0.35 μm BiCMOS technologies. Gummel plots are modelled in order to identify generation–recombination or trap-assisted tunnelling process in the base current. We show that devices having excess base current present random discrete fluctuations on the base current. The analysis of the RTS noise parameters (amplitude, high and low state time durations) as a function of temperature and bias voltage allow us to characterize the traps involved. The conventional technique consists of a statistical treatment of the RTS time domain data. The single trap capture cross-sections and activation energy are deduced with an Arrhenius plot. In order to improve the RTS analysis, we have developed an FFT-based method. The technique allows us to calculate the noise spectrum and to measure the cut-off frequency of a single trap even at very low frequencies (from 0.1 Hz). Finally, it is shown that the frequency analysis of the random telegraphic signals is a well-suited tool for the study of single defects in very small devices. Furthermore, it is complementary with conventional LFN measurements and extended to the very-low-frequency range.

Investigation of electrical characteristics of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process can be fabricated by integration of polysilicon-filled trenches. We have investigated its characteristics using I-V measurements, C-V split method and both two- and three-level charge pumping techniques. Its tunable-threshold and multi-threshold features were verified. Its surface-channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. We observed no significant degradation of these characteristics due to integration of polysilicon-filled trenches in the CMOS process.

High-

In this paper, we present measurements of the random telegraph signal (RTS) noise and the low-frequency (LF) noise in metal-oxide-semiconductor field-effect transistors (MOSFETs) integrated in silicon-on-nothing (SON) technology. This paper takes the identification of traps responsible for the drain-current fluctuations by RTS and LF techniques. We extracted the positions and the capture cross section and activation energies of oxide traps in the interfacial layer (SiO2), as well as in the high-A; dielectric (HfO2). Furthermore, it has been con vincingly shown that this discrete switching of the drain current between a high state and a low state is the basic feature responsible for the 1/fγ flicker noise in SON MOSFETs.

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We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles with a memory capacitor structure. Our approach is based on the use of indium oxide (In<inf>2</inf>O<inf>3</inf>) nanoparticles (or nanocrystals NCs) embedded in a dielectric matrix as a charge trapping layer using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. Current-voltage characteristics (I–V) showed bipolar switching behavior for all the fabricated devices, with I<inf>ON</inf>/I<inf>OFF</inf> ratios up to 10⁵. Moreover, our best structure yields up to 24 write/erase cycles, proving that our results provide insights for further integration of In<inf>2</inf>O<inf>3</inf> nanoparticles-based devices.