Francis M. Rotella

Modeling, analysis, and design of RF LDMOS devices using harmonic-balance device simulation

This paper describes how device simulation may be used for the modeling, analysis, and design of radio-frequency (RF) laterally diffused metal-oxide-semiconductor (LDMOS) transistors. Improvements to device analysis needed to meet the requirements of RF devices are discussed. Key modeling regions of the LDMOS device are explored and important physical effects are characterized. The LDMOS model is compared to dc and small-signal ac measurements for calibration purposes. Using the calibrated model, large-signal accuracy is verified using harmonic distortion simulation, and intermodulation analysis. Predictive analysis and a study of the structures parasitic components are also presented. Load-pull simulation is used to analyze matching network effects to determine the best choices for device impedance matching.

Device simulation for RF applications

The rapid growth of wireless systems at radio frequencies (RF) is driving the need for improved analog circuit and device analysis at gigaHertz frequencies. This includes: low noise front ends, linear amplifiers, mixers, and power amplifiers. Moreover, the parasitic effects of capacitance and inductance, both on- and off-chip, require careful extraction and characterization in support of predictive modeling. While time-domain techniques work well for digital systems, often the spectral and dynamic range requirements for communications systems necessitate accurate analysis of harmonic content with frequency differences of a thousandfold or more. This paper demonstrates the applicability and unique strengths of device-level harmonic balance (HB) in the simulation and physical modeling of RF circuits.

Harmonic balance device analysis of an LDMOS RF power amplifier with parasitics and matching network

This paper discusses a harmonic balance simulation involving a high power LDMOS device, bias circuitry and matching network. The paper begins with a discussion of the device and circuit configuration as well as the requirements for simulation. Next the paper describes the simulation algorithms and simulator structure in order to meet the requirements. PISCES is used as the basis and around it are added libraries for harmonic balance simulation and circuit boundary conditions. Finally, simulation results are presented. The experimental and simulated response of the power gain and power added efficiency of an RF power amplifier are shown.

Modeling and optimization of inductors with patterned ground shields for a high performance fully integrated switched tuning VCO

Pattern ground shield inductors have been shown to improve the performance of on-chip inductors by reducing the impact of the resistive substrate. This paper optimizes these inductors by separating the capacitive component and inductive component. The trade-offs are characterized and modeled. An optimized design is developed to improve the performance of a voltage controlled oscillator using a switched capacitor architecture.

Linearity Analysis of RF LDMOS Devices Utilizing Harmonic Balance Device Simulation

Linearity is one of the most important characteristics for current and next-generation RF power devices for wireless communication. In this work, linearity of power LDMOS devices is analysed by using a unique harmonic balance device simulator. Sweet-spots in the third order intermodulation distortion product (IM3) are explained and found to be in agreement with measurements and compact modeling. For demonstration of the simulation methodology, a change in the lightly doped drain (LDD) region doping concentration was performed and the effect on linearity was analysed.

Next generation Stanford TCAD-PISCES 2ET and SUPREM 007

Different aspects of Process and Device Simulators developed at Stanford are demonstrated. For PISCES 2ET, a new transport model is benchmarked in comparison to other simplified formulations. Support utilities related to curve tracing are demonstrated. The modular integration of standard tools such SUPREM 4GS and SPEEDIE with a heterogeneous set of other simulators using an agent-based approach (007) is demonstrated.<<ETX>>

Characterizing and optimizing high Q inductors for RFIC design in silicon processes

A novel metric for assessing inductor performance of advanced silicon RF process technology is proposed. The metric makes use of measured data and a verified physical model to generate a design space involving quality factor, inductance and area. Examples for technologies with top metal thickness ranging from 3 /spl mu/m to 6 /spl mu/m and dielectric thickness ranging from 4.5 /spl mu/m to 8.5 /spl mu/m are presented. Conclusions are drawn regarding the usefulness of thicker dielectrics and metal layers for RF applications in the 900 MHz to 10 GHz range.

Virtual instruments for development of high performance circuit technologies

A set of virtual instruments based on computer-aided design tools for technology (TCAD) are described. These virtual instruments support the evaluation of new technologies for circuit applications, including both intrinsic and parasitic effects. Mixed-mode (circuit/device) simulation in both the frequency and time-domain is demonstrated including an example of a virtual network analyzer applied to evaluation of a GaAs FET. Virtual curve-tracing is demonstrated as a powerful means to obtain I-V curves and to zoom in on the regions of device characteristics where SPICE model parameters can effectively be extracted and parasitic effects such as failure mechanisms due to electrostatic discharge (ESD) can be analyzed. Finally large signal distortion behavior analyzed based on the device simulation using the harmonic balance (HB) method is demonstrated with application to extraction of intermodulation (IM) distortion in bipolar transistor circuits.

Layout-based extraction of IC electrical behavior models

Behavior of IC structures is modeled using a heterogeneous set of tools and derived physical representations. A unified 3D information model is demonstrated with special emphasis on application of solid geometry modeling techniques. Examples used in this presentation include modeling of SRAM technology and interconnect structures that include packaging considerations as well. Issues of mixed level simulations are considered based on circuit and thermal constraints on IC structures.<<ETX>>

Application of BSIMSOI MOSFET model to SOS technology

The BSIMSOI model largely dominates the modeling of silicon-on-insulator (SOI) MOSFET technologies. Silicon-on-sapphire (SOS) technology has many of the advantages of SOI for RF and low-power applications, but with enhanced electrical isolation and heat dissipation, among others. We show that BSIMSOI can reasonably describe state-of-the-art SOS devices as well, including partial and full depletion, as long as differences between SOS and SOI technologies are accounted for in the parameter extraction methodology. For RF switch applications, RON and COFF are adequately represented. Also, a spot check at low currents shows that a modeled RF figure of merit, FT, is not unreasonable.