Franck Badets

A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications

This work shows a complete PLL that is integrated in standard industrial 65nm CMOS technology. This frequency synthesizer is fully compliant with IEEE 802.15.3c normalization [1–4]. This PLL delivers a quadrature LO signal around 20GHz and a differential LO signal around 40GHz and has 17.9% tuning range. The wide tuning range of 17.9% permits to cover the full IEEE 802.15.3c band with industrial margin. The phase noise is −100dBc/Hz at 1MHz offset and the total power dissipation is only 80mW including the output buffers and amplifiers. Short-range wireless multi-Gb/sec communication systems use the mm-wave band of 57GHz to 66GHz, according to the IEEE 802.15.3c normalization. The frequency synthesis is one of the key elements for these transceivers. Indeed, one must take into account the antagonist tradeoff between large band tuning range of the frequency synthesizer and phase noise performance. In transceivers using super-heterodyne architecture with double conversion, the frequency synthesizer signal fLO can be equal to 2fRF /3 and fRF /3. In this case, to cover the four channels of the IEEE 802.15.3c normalization, the frequency synthesizer has to deliver a first local oscillator (LO) signal between 19.44GHz and 21.6GHz and a second LO signal between 38.88GHz and 43.2GHz, respectively. This architecture offers a good trade off between the required large frequency tuning range (≫15%) and low phase noise (≪−95dBc/Hz).

A GHz spintronic-based RF oscillator

Wireless devices are usually based on single-frequency RF oscillators (one per band). The state-of-the-art for current technology is a combination of stand-alone high-quality, low-frequency quartz crystals resonators and integrated high-frequency, low-quality LC tank-based phase-locked loops. However, this approach now faces severe limitations in terms of integration due to CMOS scaling, power consumption, and multiple standard requirements.

HiperLAN 5.4-GHz low-power CMOS synchronous oscillator

A 5.4 GHz 0.25 /spl mu/m VLSI CMOS synchronous oscillator is proposed, which is designed to act as a local oscillator for HiperLAN systems. The design strategy is described, including the synchronization range optimization approach. A chip is presented, which provides a 150 MHz synchronization range and a -97 dBc/Hz phase noise at 10 kHz offset from the carrier, while only consuming 5 mA from a 2.5 V supply.

Advanced `Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS

A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm2 core area, achieves -108-dBm sensitivity, and -16-dBm IIP3. It is based on a discrete-time approach centering the baseband signal at half the sampling frequency. The receiver integrates Low-Noise Amplifier, filters and two 40-MHz sigma delta Analog to Digital Converters achieving a 12-bit resolution in 100 kHz.

A 56GHz LC-tank VCO with 17% tuning range in 65nm bulk CMOS for wireless HDMI applications

A voltage controlled oscillator (VCO) with 56GHz central frequency and 17% tuning range is presented. The oscillation frequency is tuned both by an analog input and a three-bit digital control bus using the same type of differential varactors. It achieves a record FOMT (considering tuning range) of 186.8 dBc/Hz and it is able to address the full wireless HDMI band. The VCO is implemented in a 65nm bulk CMOS process and dissipates 15 mW from a 1.2 V supply.

Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers

A complete analysis of the spur characteristics of edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this brief. The novelty of this analysis is the fact that it can be used to estimate the effect of both the in-lock error and the delay-stage mismatch on the spurious level of the frequency multiplier with low computational complexity. In addition, a way to reduce the mismatch between the delay cells in the delay line is discussed via an analytic model and verified by the implementation of a delay cell in a 65-nm CMOS process.

GMSK modulation of subharmonic injection locked oscillators

This paper presents theoretical results on phase modulation of injection locked oscillators. Experimental results on a 2-GHz fifth subharmonic injection locked oscillator (SBILO) integrated in a 0.35-/spl mu/m BiCMOS STMicroelectronics technology are presented. Measured phase error added by the SBILO once locked by a GMSK modulated signal is negligible.

A digitally controlled 5GHz analog phase interpolator with 10GHz LC PLL

This paper describes a 5 GHz Analog Phase Interpolator (API) for clock synthesis and clock data recovery dedicated to multi-gigabit/s serial link applications. The system includes a 10 GHz LC Phase Locked Loop for clock generation and an Analog Phase Interpolator implemented with Current Mode Logic (CML) offering better phase noise and speed performances compared to CMOS logic. It has been implemented in STs 65 nm RfCMOS technology. The core of the API occupies a silicon area of 0.09 x 0.17 mm2 and dissipates less than 22.56 mW from a 1.2 V voltage supply.

A 65-nm CMOS 8-GHz injection locked oscillator for HDR UWB applications

In this paper, an 8 GHz 16th sub-harmonic injection-locked oscillator based on LC-oscillators and pulse generators is presented. It has been fully implemented in a VLSI 65 nm CMOS technology from STMicroelectronics and is dedicated to a double-loop frequency synthesizer. Under a nominal power supply of 1.2 V, the ILO core dissipates 20mA (without buffers) for a measured phase noise of -107 dBc/Hz at 100 kHz offset from the 8 GHz carrier. It also provides a synchronization bandwidth of 350 MHz, thanks to a double synchronization network.

65nm CMOS Burst Generator for Ultra-Wideband Low Data Rate Systems

This paper presents a novel burst generator architecture dedicated to Ultra Wideband wireless communication systems based on Impulse Radio techniques. Bursts are generated by using an oscillator output signal controlled both in magnitude and phase with a high-speed digital circuit in order to limit output signal bandwidth in accordance with IEEE 802.15.4a standard requirements. The design has been integrated on a single-chip in the 65nm CMOS STMicroelectronics technology under a 1.2 V supply voltage and functionnal measurements are presented.