J.-B. Begueret

A RF circuit design methodology dedicated to critical applications

This paper presents a reliable design methodology dedicated to radio frequency integrated circuits. This methodology is based on common mask design techniques to avoid CMOS failure and on a cold standby redundancy that permits fault tolerance. The methodology has been applied to a low noise amplifier (LNA) demonstrator dedicated to ZigBee applications. The test chip has been realized in a 0.13 mum CMOS VLSI technology. The LNA provides a measured power gain of 12 clBm and a 3.6 dB noise figure, while consuming only 4 mW under a 1.2 V power supply. Measurements on the test chip demonstrate that the addition of the blocks, which achieve the reliable methodology, have no impact on the LNA performances while being efficient.