Franck Pourchon

230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications

This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-nm BiCMOS technology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to BiCMOS performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated.

A conventional double-polysilicon FSA-SEG Si/SiGe:C HBT reaching 400 GHz f MAX

This paper summarizes the work carried out to improve performances of a conventional double-polysilicon FSA-SEG SiGe:C HBT towards 400 GHz f<inf>MAX</inf>. The technological optimization strategy is discussed and electrical characteristics are presented. A record peak f<inf>MAX</inf> of 423 GHz (f<inf>T</inf> = 273 GHz) is demonstrated in SiGe:C HBT technology.

Impact of layout and technology parameters on the thermal resistance of SiGe:C HBTs

Calibrated 3-D numerical simulations supported by DC experimental data are employed to quantify the impact of the key layout and technology parameters on the thermal resistance of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) so as to define proper optimization criteria. The geometry parameters of a simple scalable model are optimized to describe the thermal resistance dependence upon emitter dimensions for the HBTs under analysis.

From measurement to intrinsic device characteristics: Test structures and parasitic determination

mm-Wave applications claim for accurate and reliable device models for their very high frequency operation range. This is not possible without any representative measurement of the intrinsic device performances especially HF small-signal measurements. In this paper we determine major parasitic contributions of regular HF test structures. Parasitic investigation goes from the probes down to the transistor. Original dummies are described and HF/DC measurements are presented and analyzed. Based on this limited set of structures a scalable de-embedding approach is described. To account for DC/HF parasitics, a sub-circuit is proposed for modeling purpose.

250-GHz self-aligned Si/SiGeC HBT featuring an all-implanted collector

This paper presents investigations led to simplify the collector module of SiGeC HBTs in order to reduce technology cost. Outcome of this work is an HBT featuring an all-implanted collector with record fT and fmax (>250 GHz)

Scalable Approach for HBT's Base Resistance Calculation

This paper presents a detailed investigation of the dual base method for intrinsic and extrinsic HBTs base resistance extraction that is of utmost importance for process monitoring and device modeling purpose. Ring emitter test structures layout, dc measurement conditions, and extraction methodology have been improved to get reliable results. A particular attention has been drawn to the external base resistance extraction and the effect of parasitic resistances is highlighted. The method has been generalized for an extraction of the base resistance specific parameters using any number of geometries (widths and lengths) and therefore demonstrates the base resistance scalability. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS SiGeC technology, and results are discussed.

A 40 GHz single-ended down-conversion mixer in 0.13 /spl mu/m SiGeC BiCMOS HBT

This work presents a single-ended active mixer realized with a 0.13 /spl mu/m BiCMOS SiGeC heterojunction bipolar transistor (HBT) technology. This mixer is designed to be integrated in a superheterodyne receiver for 40 GHz wireless communication systems. Local oscillator (LO) and RF signals are directly applied to the base of the HBT through two coupled lines. The mixer provides a down-conversion from 42 GHz to 2 GHz. The mixer exhibits a power conversion gain better than 2.4 dB and a measured double-sideband noise figure less than 8.3 dB for P/sub LO/=3 dBm (power of the local oscillator) under a global power consumption lower than 9.5 mW. This architecture exhibits good linearity performance with a measured IP/sub 1dB/ of about -7 dBm and an IIP3 of +4 dBm. The linear dynamic range for a 2 GHz system bandwidth is approximately 65 dB for P/sub LO/=+2 dBm and T/sub 0/=290 K. The third order spurious free dynamic range is calculated to be better than 52 dB.

Application of on-wafer calibration techniques for advanced high-speed BiCMOS technology

On-wafer RF calibration methods are compared to the conventional Impedance Standard Substrate (ISS) calibration combined with a dummies de-embedding approach for transistors of an advanced BiCMOS process. We discuss the design of customized calibration standards addressing specifics of the silicon BiCMOS process. Our results show that on-wafer calibration methods are the most suitable approaches for accurate characterization of sub-THz SiGe HBTs.

High frequency mismatch characterization on 170GHz HBT NPN bipolar device

This paper describes a high frequency mismatch approach on BJT able to reach Ft=170GHz. All obtained results are complementary and all well linked with the mismatch extract from DC measurement and in good agreement with the model parameters. In order to extract these results, a new test structure and associated parameter extraction tool have been developed.

Scalable approach for external collector resistance calculation

For device modelling purposes, the geometry dependence of the external collector resistance has been investigated. Firstly, the collector resistance is split into a perfectly 1D vertical resistance and a 2D horizontal contribution. Using specific test structures and DC measurements, geometry independent parameters are then extracted. An analytical scalable formula based on Fourier techniques finally computes both components for a given geometry by taking into account the current distribution in the horizontal layer. This new method is applied to a double poly BiCMOS technology and results are discussed.