François M. Klaassen

Compact transistor modelling for circuit design

This text describes analytical compact transistor models that can be used in circuit simulation programs like SPICE. It provides the reader with a thorough knowledge of many aspects of compact models. The book starts with the necessary device physics: Boltzmann transport equation; continuity equation; Poisson equation; and physical modelling of mobility, recombination, bandgap narrowing, avalanche multiplication and noise. Then, a systematic treatment of the analytical formulas that describe the device behaviour in DC, AC and transient situations is given for both bipolar and MOST devices. The book contains complete sets of model equations for various models, including some new ones, and special attention is paid to the numerical problems of analytical continuity. Separate chapters are devoted to parameter determination, the parameter temperature dependence, as well as their relation to process variables, the statistical correlations between parameters, the scaling rules for submicron devices, the side-wall effects and the parasitics.

Device physics of integrated injection logic

After a brief review of relevant device parameters, characterizing the inversely operating multicollector n-p-n transistor and the lateral p-n-p transistor which make up anI^{2}Lbasic cell, some electronic circuit properties of this gate are discussed quantitively. Analytic expressions are derived for the transfer characteristics, the noise margin and the propagation delay time per gate in relation to the cell geometry, fan-out, doping profiles, and recombination properties. These expressions are compared with experimental and numerical circuit simulation results.

Effect of gate-field dependent mobility degradation on distortion analysis in MOSFETs

Compact MOSFET models in contemporary circuit simulators fail to accurately describe distortion effects. In the ohmic region of the MOSFET, this failure is mainly due to inaccurate modeling of the gate-field dependent mobility degradation effect. In this paper a new model for mobility degradation Is introduced which gives a major improvement in distortion analysis in the linear region for both n-type and p-type MOS transistors. Incorporating a gate voltage dependent series resistance, this model even gives good results for very short channel length devices.

High-frequency noise of the junction field-effect transistor

Based on Geursts treatment of the high-frequency value of the admittances of the junction field-effect transistor, the high-frequency noise of the device has been computed, assuming that the noise source is of thermal origin. By applying an appropriate series expansion of the current it is possible to express the noise of the drain and gate current in terms of known quantities, as steady-state transconductance, gate capacitance, and frequency. At low frequencies the noise spectrum of the drain current is independent of the frequency and is much larger than the noise of the gate current; however, at high frequencies the noise spectra of the gate and drain current both vary by ω2and are of the same order of magnitude.

On the influence of hot carrier effects on the thermal noise of field-effect transistors

The noise resistance of the field-effect transistor has been calculated taking into account high-field effects such as mobility saturation and hot carrier temperature upon the thermal noise. The result of the calculations can be represented by a practical formula. The calculated results have been compared with measurements of the noise of a junction gate FET and a MOS tetrode with short active channels. The agreement is reasonable. At room temperature the effect is moderate, but at low temperatures it is considerable.

A novel technique to determine the gate and drain bias dependent series resistance in drain engineered MOSFETs using one single device

A new measurement method is explained for the extraction of the source and drain series resistance of drain engineered MOSFETs from their low frequency ac characteristics as a function of gate and drain bias using only one single MOSFET. Experimental results indicate, the effect of drain voltage dependent series resistance is relevant both in the ohmic and in the saturation region of the MOSFET. In addition the new measurement method is extended in such a way that it can be used to measure the series resistance as a function of gate bias only at low drain bias. Comparison of this single transistor measurement technique with other methods, needing a set of identical transistors with different channel lengths, shows that our method gives equal results. Finally attention is also given to the modeling of the series resistance in the ohmic and saturation region. For both regions simple, accurate compact model expressions have been derived.

Noise of field-effect transistors at very high frequencies

The minimum noise factor of a field-effect transistor has been computed at high frequencies on the basis of the thermal noise of the real parts of the equivalent circuit. A treatment of the intrinsic FET is followed by a consideration of the influence of feedback, parasitic output impedance and parasitic impedance in series with the source on the noise factor. Moreover, the difference between common-gate and common-source configuration has been considered. For frequencies smaller than the gain-bandwidth product f gb the factor F_{\min} - 1 varies linearly with the frequency, whereas at higher frequencies this factor varies with f2. The computed results are compared with measurements on both JFETs and MOSFETs in the frequency range 100-1500 MHz at different conditions of operation. The agreement is rather good. For the JFET the value of F_{\min}(f_{gb}) \approx 2.5 ; for the MOSFET somewhat higher values are found due to the presence of substrate depletion effects.

Comments on hot carrier noise in field-effect transistors

Taking into account more rigorously such high field effects as velocity saturation and an increasing free carrier temperature, a new derivation is presented for the output noise of the field-effect transistor. It is shown that for devices with a short channel and a high saturation voltage the equivalent noise resistance can increase considerably above the low field value.

Lateral pnp Transistor Models

The use of lateral pnp transistors is widespread in linear integrated circuits. They are applied as active load devices, current sources, level shifters etc. [5.1]. Furthermore they are an integral part of integrated injection logic (I 2 L) circuits [5.2].

Process and Geometry Dependence, Optimization and Statistics of Parameters

The parameters of a compact model are in general dependent on the geometry of the device and on the technological process steps. The geometry of the device is mainly characterized by the lateral dimensions of the junctions in bipolar transistors and by the channel length and width in MOS transistors. The dimensions must be known in silicon because only the real dimensions are electrically significant. They are determined by the dimensions of the mask, corrected for such effects as outdiffusion, underetching, misalignment of masks, encroachment of isolation oxides, etc.