Frank Bouwens

A 2.4 GHz ULP OOK Single-Chip Transceiver for Healthcare Applications

This paper describes an ultra-low power (ULP) single chip transceiver for wireless body area network (WBAN) applications. It supports on-off keying (OOK) modulation, and it operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands. It is implemented in 90 nm CMOS technology. The direct modulated transmitter transmits OOK signal with 0 dBm peak power, and it consumes 2.59 mW with 50% OOK. The transmitter front-end supports up to 10 Mbps. The transmitter digital baseband enables digital pulse-shaping to improve spectrum efficiency. The super-regenerative receiver front-end supports up to 5 Mbps with -75 dBm sensitivity. Including the digital part, the receiver consumes 715 μW at 1 Mbps data rate, oversampled at 3 MHz. At the system level the transceiver achieves PER=10 -2 at 25 meters line of site with 62.5 kbps data rate and 288 bits packet size. The transceiver is integrated in an electrocardiogram (ECG) necklace to monitor the hearts electrical property.

Architectural exploration of the ADRES coarse-grained reconfigurable array

Reconfigurable computational architectures are envisioned to deliver power efficient, high performance, flexible platforms for embedded systems design. The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer a tool flow to design sparsely interconnected 2D array processors with an arbitrary number of functional units, register files and interconnection topologies. This article presents an architectural exploration methodology and its results for the first implementation of the ADRES architecture on a 90nm standard-cell technology. We analyze performance, energy and power trade-offs for two typical kernels from the multimedia and wireless domains: IDCT and FFT. Architecture instances of different sizes and interconnect structures are evaluated with respect to their power versus performance trade-offs. An optimized architecture is derived. A detailed power breakdown for the individual components of the selected architecture is presented.

Architecture enhancements for the ADRES coarse-grained reconfigurable array

Reconfigurable architectures provide power efficiency, flexibility and high performance for next generation embedded multimedia devices. ADRES, the IMEC Coarse-Grained Reconfigurable Array architecture and its compiler DRESC enable the design of reconfigurable 2D array processors with arbitrary functional units, register file organizations and interconnection topologies. This creates an enormous design space making it difficult to find optimized architectures. Therefore, architectural explorations aiming at energy and performance trade-offs become a major effort. In this paper we investigate the influence of register file partitions, register file sizes and the interconnection topology of ADRES. We analyze power, performance and energy delay trade-offs using IDCT and FFT as benchmarks while targeting 90nm technology. We also explore quantitatively the influences of several hierarchical optimizations for power by applying specific hardware techniques, i.e. clock gating and operand isolation. As a result, we propose an enhanced architecture instantiation that improves performance by 60 - 70% and reduces energy by 50%.

A 2.4GHz ULP OOK single-chip transceiver for healthcare applications

Wireless body-area networks (WBAN) are used for communication among sensor nodes operating on, in or around the human body, e.g. for healthcare purposes. In view of energy autonomy, the total energy consumption of the sensor nodes should be minimized. Because of their low complexity, a combination of the super-regenerative (SR) principle [1–3] and OOK modulation enables ultra-low power (ULP) consumption. This work presents a 2.4GHz ULP OOK singlechip transceiver for WBAN applications. A block diagram of the implemented transceiver is shown in Fig. 26.3.1. Next to the direct modulation TX [4] and SR RF [5] front-ends, this work integrates analog and digital baseband, PLL functionality and additional programmability for flexible data rates, and achieves ultra-low power consumption for the overall system.

Ultra Low Power programmable biomedical SoC for on-body ECG and EEG processing

An Ultra Low Power (ULP) biomédical System-on-Chip (SoC) has been developed for efficient ECG/EEG signal processing in a Body Area Network environment. This experimental SoC explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set-Processor (ASIP) to optimize energy-efficiency during active and sleep periods. The SoC has been manufactured in standard 90nm CMOS process and use has been made of power gating to reduce leakage power that starts to become more dominant in advanced technologies. When running an ECG algorithm that is capable of reliably detecting the QRS complex in an ambulatory environment, an average power consumption of 10 μW has been measured at 0.7 V supply.

Ultra Low Power ASIP Design for Wireless Sensor Nodes

This work presents a methodology for designing an ultra low power application specific instruction set processor. This paper shows the different steps to develop a digital signal processing architecture for a single channel ECG application assuming a system level power dissipation constraint of 100 muW. We follow a bottleneck driven approach based on the following steps. First coarse grained clock gating is applied. Next, the static as well as the dynamic dissipation of the digital processor is reduced and possibilities for future improvements are discussed. Finally, an optimal processor is built consuming 8.40 muW when running the reference application.

Energy-autonomous wireless vibration sensor for condition-based maintenance of machinery

This paper addresses the development of an energy-autonomous wireless vibration sensor for condition-based monitoring of machinery. Such technology plays an increasingly important role in modern manufacturing industry. In this work, energy harvesting is realized by resorting to a custom designed thermoelectric generator. The developed wireless vibration sensor has a remotely tunable sampling rate, which caters to the different needs of various operating conditions. The two key features, energy autonomy and wireless measurement, are demonstrated successfully by the experimental results obtained on the thermoelectric generator and the wireless sensor.

A dual-core system solution for wearable health monitors

This paper presents a system design study for wearable sensor devices intended for healthcare and lifestyle applications based on ECG, EEG and activity monitoring. In order to meet the low-power requirement of these applications, a dual-core signal processing system is proposed which combines an ultra-low-power bio-medical Application Specific Instruction-set Processor (BioASIP) and a low-power general-purpose micro-controller (MSP430). To validate the merits of the proposed architecture, system-level power analysis and trade-offs are conducted using real hardware measurements of an ECG R-peak detection application. The results show that the proposed dual-core architecture consumes around 65.38µW, about 25.8x smaller than an MSP430-only approach. Out of 65.38µW, the BioASIP consumes only 11µW and the rest is used in the analog front-end, A/D conversion, and control tasks.

Wireless vibration monitoring on human machine operator

Human machine operators are often subject to extreme shocks and vibrations while operating production machines and vehicles. To assess the impact on perceived comfort objectively, a wireless vibration monitoring system is needed that measures whole-body vibrations directly on the human body. To this end, we have developed a wireless body area network consisting of low-power vibration sensor nodes that have a small and ergonomic form factor and that are easy to install. Furthermore, we have validated the BAN along with the necessary post-processing of the raw vibration signals on a real industrial case, i.e. the driver of a forklift. Our system proves to be instrumental in optimizing critical tuning parameters of a machine, exemplified by the transmission control parameters of a forklift.

Design of 100 µW wireless sensor nodes on energy scavengers for biomedical monitoring

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogram application, which is used as an application example. We aim for less than 100µW power consumption as that is the power energy scavengers can deliver. We follow a bottleneck-driven approach, the following steps are applied: first the algorithm is tuned to the target processor, then coarse grained clock-gating is applied, next the static as well as the dynamic dissipation of the digital processor is reduced by tuning the core to the target domain. The impact of each step is quantified. A solution of around 11µW is possible for both radio and DSP with the electrocardiogram algorithm.