Jos Hulzink

A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V

Recent work on designing ultra-low-power systems has focused on the sub-threshold regime [1–3] and an energy efficiency of a few pJ/cycle was reported. While operating at the minimum energy point is attractive for energy-frugal devices like those used for wireless biomedical signal monitoring, the achieved clock frequency is usually in the kHz range. The low frequency combined with limited processing capacity, small on-chip memory, and low computation precision prevents the use of these systems for complex ambulatory monitoring beyond a simple ECG algorithm. Low-voltage systems with more computational power are demonstrated in [4] and [5].

An Ultra Low Energy Biomedical Signal Processing System Operating at Near-Threshold

This paper presents a voltage-scalable digital signal processing system designed for the use in a wireless sensor node (WSN) for ambulatory monitoring of biomedical signals. To fulfill the requirements of ambulatory monitoring, power consumption, which directly translates to the WSN battery lifetime and size, must be kept as low as possible. The proposed processing platform is an event-driven system with resources to run applications with different degrees of complexity in an energy-aware way. The architecture uses effective system partitioning to enable duty cycling, single instruction multiple data (SIMD) instructions, power gating, voltage scaling, multiple clock domains, multiple voltage domains, and extensive clock gating. It provides an alternative processing platform where the power and performance can be scaled to adapt to the application need. A case study on a continuous wavelet transform (CWT)-based heart-beat detection shows that the platform not only preserves the sensitivity and positive predictivity of the algorithm but also achieves the lowest energy/sample for ElectroCardioGram (ECG) heart-beat detection publicly reported today.

Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS

Wireless Sensor Nodes (WSN) have a wide range of applications in health care and life style monitoring. Their severe energy constraint is often addressed through minimizing the amount of transmitted data by way of energy-efficient on-node signal processing. The rationale for this approach is that a large portion of WSN energy is consumed by the radio communication even for very low-data-rate situations [1]. Efficient on-node processing has been the subject of recent work, with the common element being aggressive voltage scaling into the sub-threshold region [2-4]. A major assumption of the existing works is that the amount of required computation is low, justifying an on-node processor with limited computational capability. While this might be the case for many applications of WSNs, emerging ambulatory biomedical signal processing applications exceed the performance offered by todays on-node processors.

Ultra Low Power programmable biomedical SoC for on-body ECG and EEG processing

An Ultra Low Power (ULP) biomédical System-on-Chip (SoC) has been developed for efficient ECG/EEG signal processing in a Body Area Network environment. This experimental SoC explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set-Processor (ASIP) to optimize energy-efficiency during active and sleep periods. The SoC has been manufactured in standard 90nm CMOS process and use has been made of power gating to reduce leakage power that starts to become more dominant in advanced technologies. When running an ECG algorithm that is capable of reliably detecting the QRS complex in an ambulatory environment, an average power consumption of 10 μW has been measured at 0.7 V supply.

Ultra Low Power ASIP Design for Wireless Sensor Nodes

This work presents a methodology for designing an ultra low power application specific instruction set processor. This paper shows the different steps to develop a digital signal processing architecture for a single channel ECG application assuming a system level power dissipation constraint of 100 muW. We follow a bottleneck driven approach based on the following steps. First coarse grained clock gating is applied. Next, the static as well as the dynamic dissipation of the digital processor is reduced and possibilities for future improvements are discussed. Finally, an optimal processor is built consuming 8.40 muW when running the reference application.

Exploration of cryptographic ASIP designs for wireless sensor nodes

We present the design of 4 Application Specific Instruction Set Processors (8-bit, 32-bit, 64-bit and 128-bit ASIP) which provide typical 16-bit general instructions and accelerate a common cryptographic domain. The ASIPs support the following security services: data confidentiality, data authentication, data integrity and replay attack protection and their design is appropriate for wireless sensor networks. The corresponding software for each ASIP has been optimized in terms of clock cycles and memory accesses. We evaluate the 4 ASIPs in terms of performance, power consumption, energy dissipation and area occupation. When our most energy efficient design (128-bit ASIP) operates on AES-CCM-32 security mode at a clock frequency of 100 MHz, it dissipates 41.86 nJ achieving a maximum throughput of 21.76 Mbps, while at a lower clock frequency of 4.61 MHz, it achieves a throughput of 1 Mbps, a typical value in the WSN, and dissipates energy of 35.20 nJ. The corresponding area overhead, for 90nm technology, excluding the memories, is 34.3K NAND2 equivalents. Comparisons with other works are given.

Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm

High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, one can improve the computing power by introducing special purpose hardware units. In this paper, we present a case study with a possible design methodology for an ultra low power application specific instruction-set processor. A cardiac beat detector algorithm based on the Continuous Wavelet Transform is implemented in the C language. This application is further optimized using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies, and the processor is further optimized for ultra low power consumption by applying application specific hardware, and by using several hardware optimization techniques. The optimized processor is compared with the unoptimized version, resulting in a 55% reduction in power consumption. The reduction in the total execution cycle count is 81%. Power gating, and dynamic voltage and frequency scaling, are investigated for further power optimization. For a given case, the reduction in the already optimized power consumption is estimated to be 62% and 35%, respectively.

A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing

The IEEE 802.15.4a amendment has introduced ultra-wideband impulse radio (UWB IR) as a promising physical layer for energy-efficient, low data rate communications. A critical part of the UWB IR receiver design is the low-power implementation of the digital baseband processing required for synchronization and data decoding. In this paper we present the development of an application-specific instruction-set processor (ASIP) that is tailored to the requirements defined by the baseband algorithms. We report a number of optimizations applied to the algorithms as well as to the hardware architecture. This enables performance increases up to a factor of 122x and energy consumption decreases up to 90x as compared to a 16-bit baseline architecture. Furthermore, this ASIP offers greater flexibility due to programmability as compared to an ASIC implementation.

Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing

The advent of the mobile age has heavily changed the requirements of todays communication devices. Data transmission over interference-prone wireless channels requires additional steps of data processing, such as forward error correction, to ensure reliable communication. In this work we present RS(63,55) Reed-Solomon encoding and decoding algorithms according to the IEEE 802.15.4a standard executed on dedicated application-specific processor architectures. Algorithmic as well as architectural modifications to speed up execution and well-known low-power techniques to reduce the power consumption are discussed. The speed-up for our proposed designs compared to a general purpose baseline architecture is up to two orders of magnitude. Power reduction due to clock-gating and guarded evaluation results in a 40% power drop and the energy consumption is decreased up to 60x.

A 36μW heartbeat-detection processor for a wireless sensor node

In order to provide better services to elderly people, home healthcare monitoring systems have been increasingly deployed. Typically, these systems are based on wireless sensor nodes, and should utilize very low energy during their lifetimes, as they are powered by scavengers. In this article, we present an ultra-low power processing system for a wireless sensor node for very low duty cycle applications. In the CoolBio system-on-chip, we utilized several power reduction techniques at both the architecture level and the circuit level. These techniques include feature extraction, voltage and frequency scaling, clock and power gating and a redesign of key standard cells. In the design of the ultra-low power processing system, we paid special attention to the memory subsystem, as it is one of the most power-consuming modules in a design. We also designed a clock manager in order to reduce the power consumed by clocking, and a power manager that is able to power-off unutilized modules. The proposed wireless sensor node processing system consumes 36.4μW at 100MHz and 1.2V supply voltage, for a heartbeat-detection algorithm with a 0.01% duty cycle.