Frank J. Rueß

The use of etched registration markers to make four-terminal electrical contacts to STM-patterned nanostructures.

We demonstrate the use of etched registration markers for the alignment of four-terminal ex situ macroscopic contacts created by conventional optical lithography to buried nanoscale Si:P devices, patterned by hydrogen-based scanning tunnelling microscope (STM) lithography. Using SiO(2) as a mask we are able to protect the silicon surface from contamination during marker fabrication and can achieve atomically flat surfaces with atomic-resolution imaging. The registration markers are shown to withstand substrate heating to approximately 1200 degrees C and epitaxial overgrowth of approximately 25 nm Si. Using a scanning electron microscope to position the STM tip with respect to the markers, we can achieve alignment accuracies of approximately 100 nm, which allows us to contact buried Si:P structures. We have applied this technique to fabricate P-doped wires of different widths and measured their I-V characteristics at 4 K, finding ohmic behaviour down to a width of approximately 27 nm.

Narrow, highly P-doped, planar wires in silicon created by scanning probe microscopy

We demonstrate the use of a scanning tunnelling microscope (STM) to pattern buried, highly planar phosphorus-doped silicon wires with widths down to the sub-10 nm level. We confirm the structural integrity of these wires using both buried dopant imaging techniques and ex situ electrical characterization. Four terminal I–V characteristics at 4 K show ohmic behaviour for all wires with resistivities between 1 and 24 × 10−8 Ω cm. Magnetotransport measurements reveal that conduction is dominated by disordered scattering with quantum corrections consistent with 2D weak localization theory. Our results show that these quantum corrections become more pronounced as the electron phase coherence length approaches the width of the wire.

Surface gate and contact alignment for buried, atomically precise scanning tunneling microscopy–patterned devices

The authors have developed a complete electron beam lithography (EBL)-based alignment scheme for making multiterminal Ohmic contacts and gates to buried, planar, phosphorus-doped nanostructures in silicon lithographically patterned by scanning tunneling microscopy (STM). By prepatterning a silicon substrate with EBL-defined, wet-etched registration markers, they are able to align macroscopic contacts to buried, conducting STM-patterned structures with an alignment accuracy of ∼100nm. A key aspect of this alignment process is that, by combining a circular marker pattern with step engineering, they are able to reproducibly create atomically flat, step-free plateaus with a diameter of ∼300nm so that the active region of the device can be patterned on a single atomic Si(100) plane at a precisely known position. To demonstrate the applicability of this registration strategy, they show low temperature magnetoresistance data from a 50nm wide phosphorus-doped silicon nanowire that has been STM-patterned onto a si...

Confinement and integration of magnetic impurities in silicon

Integration of magnetic impurities into semiconductor materials is an essential ingredient for the development of spintronic devices such as dilute magnetic semiconductors. While successful growth of ferromagnetic semiconductors was reported for III-V and II-VI compounds, efforts to build devices with silicon technology were hampered by segregation and clustering of magnetic impurities such as manganese (Mn). Here, we report on a surface-based integration of Mn atoms into a silicon host. Control of Mn diffusion and low-temperature silicon epitaxy lead to confined Mn δ-layers with low interface trap densities, potentially opening the door for a new class of spintronic devices in silicon.

Effective removal of hydrogen resists used to pattern devices in silicon using scanning tunneling microscopy

We present a high resolution scanning tunneling microscope (STM) study of the thermal desorption of hydrogen resist layers used for STM-based lithography on the Si(001)2×1 surface. From this study we determine the optimum annealing conditions for removing the hydrogen resist in one step. We demonstrate that this thermal process can completely remove the hydrogen resist from a phosphorus doped surface structure created using STM-lithography, without disturbing the lithographically defined structure. We investigate the effectiveness of the removal process by performing electrical measurements of a buried STM-patterned device created using the optimized thermal desorption process and demonstrate that we can achieve phase coherence lengths of ∼40nm, comparable to that in P in Si delta-doped layers where no hydrogen resist or STM patterning has been used.

Comparison of GaP and PH3 as dopant sources for STM-based device fabrication

We present a comparative study of the use of a GaP solid source as an alternative to gaseous PH3 for controlled phosphorus δ-doping of lithographic patterns on H:Si(001) fabricated by scanning tunnelling microscopy (STM). Whilst our electrical studies show that P δ-doping of Si with the GaP solid source and gaseous PH3 result in essentially the same electrical characteristics, our STM studies reveal that P2 molecules from the GaP source exhibit a lower selectivity between bare Si(001) and H:Si(001) compared to PH3 molecules. We discuss the significance of our findings in the context of fabricating nanoscale P dopant devices in Si using STM-based lithography.

Ohmic conduction of sub-10nm P-doped silicon nanowires at cryogenic temperatures

We investigate the conduction properties of an embedded, highly phosphorus-doped nanowire with a width of 8nm lithographically defined by scanning tunneling microscope based patterning of a hydrogen-terminated Si(100):H surface. Four terminal I-V measurements show that ohmic conduction is maintained within the investigated temperature range from 35K down to 1.3K. A prominent resistance increase is observed below ∼4K which is attributed to a crossover into the strong localization regime. The low temperature conductance follows a one-dimensional variable range hopping model accompanied by positive magnetoresistance which dominates over weak localization effects at low temperature.

Structural and electrical characterization of room temperature ultra-high-vacuum compatible SiO2 for gating scanning tunneling microscope-patterned devices

We present an ultrahigh vacuum technique for depositing SiO2 at room temperature using an atomic oxygen source and Si coevaporation for ultimate use as a dielectric for gating Si devices with atomically precise dopant profiles. The resulting SiO2 layers were characterized in situ by scanning tunneling microscopy, ex situ by transmission electron microscopy and ellipsometry and integrated as the gate dielectric in a metal oxide semiconductor field effect transistor (MOSFET). The electrical characteristics of the MOSFETs were investigated at 4.2K, giving an interface trap density of ∼1011cm−2 from conductance and Hall effect measurements.

Electrical properties of atomically controlled Si:P nanowires created by scanning probe microscopy

We report on the electrical properties of highly phosphorus‐doped, planar nanowires with widths of 90, 50 and 27 nm. I‐V measurements at 4 K show that all wires are highly ohmic with resistivities as low as 1 × 10−8 Ωcm. Magnetotransport measurements are consistent with 2D weak localization theory and demonstrate an increasing contribution to conductance as the electron phase coherence length approaches the wire width.