Wilson Pok

Atomic-scale silicon device fabrication

The driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce device sizes below 10 nm. In this paper we demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in combination with scanning probe lithography and high purity crystal growth. Using this process we have fabricated conducting nanoscale wires with widths down to ∼8 nm, and arrays of P-doped dots in silicon. We will present an overview of devices that have been made with this technology and highlight some of the detailed atomic level understanding of the doping process developed towards atomically precise devices.

Epitaxial top-gated atomic-scale silicon wire in a three-dimensional architecture

Three-dimensional (3D) control of dopant profiles in silicon is a critical requirement for fabricating atomically precise transistors. We demonstrate conductance modulation through an atomic scale 3 nm wide δ-doped silicon-phosphorus wire using a vertically separated epitaxial doped Si:P top-gate. We show that intrinsic crystalline silicon grown at low temperatures (∼250 °C) serves as an effective gate dielectric permitting us to achieve large gate ranges (∼2.6 V) with leakage currents below 1 pA. Combining scanning tunneling lithography for precise lateral confinement, with monolayer doping and low temperature epitaxial overgrowth for precise vertical confinement, we can realize multiple layers of nano-patterned dopants in a single crystal material. These results demonstrate the viability of highly doped, vertically separated epitaxial gates in an all-crystalline architecture with long-term implications for monolithic 3D silicon circuits and for the realization of atomically precise donor architectures for quantum computing.

Electrical Characterization of Ordered Si:P Dopant Arrays

We report on the ability to fabricate arrays of planar, nanoscale, highly doped phosphorus dots in silicon separated by source and drain electrodes using scanning tunneling microscope lithography. We correlate ex situ electrical measurements with scanning tunneling microscope (STM) images of these devices and show that ohmic conduction can be achieved through the disordered array with a P coverage of 0.8times1014 cm-2. In comparison, we show that an ordered array of P dots ~6 nm in diameter and containing ~50 P atoms separated by ~4 nm shows nonlinear I-V, characteristic of a series of metallic dots separated by tunnel barriers. These results highlight the use of STM lithography to pattern ordered dopants in silicon down to the sub-10 nm scale

Morphology and electrical conduction of Si:P δ-doped layers on vicinal Si(001)

We present a combined scanning tunneling microscopy (STM) and low-temperature magnetotransport study of Si:P δ-doped layers on vicinal Si(001) substrates. The substrates were misoriented 4° toward [110] resulting in a high step density on the starting growth surface. Atomically resolved STM was used to study all stages of the fabrication. We find only a weak influence of the high step density and discuss the implications for the fabrication δ-doped layers and planar nanoscale Si:P devices by scanning tunneling lithography.

Ohmic conduction of sub-10nm P-doped silicon nanowires at cryogenic temperatures

We investigate the conduction properties of an embedded, highly phosphorus-doped nanowire with a width of 8nm lithographically defined by scanning tunneling microscope based patterning of a hydrogen-terminated Si(100):H surface. Four terminal I-V measurements show that ohmic conduction is maintained within the investigated temperature range from 35K down to 1.3K. A prominent resistance increase is observed below ∼4K which is attributed to a crossover into the strong localization regime. The low temperature conductance follows a one-dimensional variable range hopping model accompanied by positive magnetoresistance which dominates over weak localization effects at low temperature.

Structural and electrical characterization of room temperature ultra-high-vacuum compatible SiO2 for gating scanning tunneling microscope-patterned devices

We present an ultrahigh vacuum technique for depositing SiO2 at room temperature using an atomic oxygen source and Si coevaporation for ultimate use as a dielectric for gating Si devices with atomically precise dopant profiles. The resulting SiO2 layers were characterized in situ by scanning tunneling microscopy, ex situ by transmission electron microscopy and ellipsometry and integrated as the gate dielectric in a metal oxide semiconductor field effect transistor (MOSFET). The electrical characteristics of the MOSFETs were investigated at 4.2K, giving an interface trap density of ∼1011cm−2 from conductance and Hall effect measurements.

Atomically precise silicon device fabrication

An important driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce devices below 10 nm. We demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in combination with scanning probe lithography and high purity, low temperature crystal growth. A major advantage of this strategy is the ability to investigate the role of dopant placement and atomically controlled growth on electronic device operation.