Frank Liu

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The effectiveness of our method is comprehensively demonstrated with the International Symposium on Circuits and Systems (ISCAS) benchmarks and a 65-nm industrial design. Furthermore, we extract the following key design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; 2) There is an optimum supply voltage that leads to the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is highly sensitive to input vectors. The difference in delay degradation is up to 5× for various static and dynamic operations. Finally, we examine the interaction between NBTI effect, and process and design uncertainty in realistic conditions.

The impact of NBTI on the performance of combinational and sequential circuits

Negative-bias-temperature-instability (NBTI) has become the primary limiting factor of circuit lifetime. In this work, we develop a general framework for analyzing the impact of NBTI on the performance of a circuit, based on various circuit parameters such as the supply voltage, temperature, and node switching activity of the signals etc. We propose an efficient method to predict the degradation of circuit performance based on circuit topology and the switching activity of the signals over long periods of time. We demonstrate our results on ISCAS benchmarks and a 65 nm industrial design. The framework is used to provide key design insights for designing reliable circuits. The key design insights that we obtain are: (1) degradation due to NBTI is most sensitive on the input patterns and the duty cycle; the difference in the delay degradation can be up to 5X for various static and dynamic conditions, (2) during dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; (3) NBTI has marginal impact on the clock signal.

A Test Structure for Characterizing Local Device Mismatches

We present a test structure for statistical characterization of local device mismatches. The structure contains densely populated SRAM devices arranged in an addressable manner. Measurements on a test chip fabricated in an advanced 65 nm process show little spatial correlation. We vary the nominal threshold voltage of the devices by changing the threshold-adjust implantations and observe that the ratio of standard deviation to mean gets worse with threshold scaling. The large variations observed in the extracted threshold voltage statistics indicate that the random doping fluctuation is the likely reason behind mismatch in the adjacent devices

A general framework for spatial correlation modeling in VLSI design

Many characteristics of VLSI designs, such as process variations, demonstrate strong spatial correlations. Accurately modeling of these correlated behaviors is crucial for many timing and power analyses to be valid. This paper proposes a new spatial model with a long-range trend component, a smooth correlation component, as well as a truly random component. The efficient method to construct such a spatial model is based on the Generalized Least Square fitting and the structured correlation functions, which are actually the generalization of the popular Pelgrom mismatch models. Experimental results on industrial benchmarks show that the method is not only highly effective for variability modeling, but can also be used for other spatially distributed characteristics such as IR drops and on-chip temperature distributions.

Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction

Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parametric interconnect models is often hampered by the rapid increase in computational cost and model complexity. In this paper we present an efficient yet accurate parametric model order reduction algorithm for addressing the variability of IC interconnect performance. The efficiency of the approach lies in a novel combination of low-rank matrix approximation and multi-parameter moment matching. The complexity of the proposed parametric model order reduction is as low as that of a standard Krylov subspace method when applied to a nominal system. Under the projection-based framework, our algorithm also preserves the passivity of the resulting parametric models.

A delay metric for RC circuits based on the Weibull distribution

Physical synthesis optimizations require fast and accurate analysis of RC networks. Elmore first proposed matching circuit moments to a probability density function (PDF), which led to widespread adoption of his simple and fast metric. The more recently proposed PRIMO and H-gamma metrics match the circuit moments to the PDF of a Gamma statistical distribution. We instead propose to match the circuit moments to a Weibull distribution and derive a new delay metric called Weibull-based delay (WED). The primary advantages of WED over PRIMO and H-gamma are its efficiency and ease of implementation. Experiments show that WED is robust and has satisfactory accuracy at both near- and far-end nodes.

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness

The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical design. In this work, we develop an efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by lithography and the etching process. By understanding the physical principles of atomistic simulations, we: 1) identify the appropriate method to divide a nonuniform gate into slices in order to map those fluctuations into the device model; 2) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth ; 3) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations; and 4) investigate the interaction with non-rectangular gate (NRG) and reverse narrow width effect (RNWE). The proposed SPICE simulation method is validated with atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, helping shed light on the challenges of future robust circuit design.

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees

Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these formulae assume a step excitation, leaving it to the reader to find a suitable extension to ramp-we always refer to saturated ramps in this paper-inputs. The few works that do consider ramp inputs do not present a closed-form formula that works for a wide range of possible input slews. We propose the PERI (probability distribution function extension for ramp inputs) technique, that extends delay metrics for step inputs to the more general and realistic non-step (such as a ramp) inputs. Although there has been little work done in finding good slew (which is also referred as signal transition time) metrics, we also show how one can extend a slew metric for step inputs to the non-step case. We validate the efficacy of our approach through experimental results from several hundred RC dominated nets extracted from an industry application specific integrated circuit design.

Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness

The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive computationally for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth and (c) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, to help shed light on the challenges of future robust circuit design.

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits

Input vector control has been used to minimize the leakage powerconsumption of a circuit in sleep state. In this paper, we presenta novel heuristic for determining a low leakage vector to beapplied to a circuit in sleep state. The heuristic is a greedy searchbased on the controllability of nodes in the circuit and uses thefunctional dependencies among cells in the circuit to guide thesearch. Results on a set of ISCAS and MCNC benchmark circuitsshow that in all cases our heuristic returns a vector having aleakage within 5% of that of the vector obtained using an extensiverandom search, with orders of magnitude improvement incomputational speed.