Kanak B. Agarwal

Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating

The exponential increase in leakage power due to technology scaling has made power gating an attractive design choice for low-power applications. In this paper, we explore this design style in large combinational circuit blocks and latch-to-latch datapaths and introduce a novel power gating approach to yield an improved power-performance tradeoff. We first present a multiple sleep mode power gating technique where each mode represents a different point in the wake-up overhead versus leakage savings design space. We show that the high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. The multiple-mode feature allows a processor to enter power saving modes more frequently, hence, resulting in enhanced leakage savings. We apply the multimode power gating technique to datapaths where the degree of applied power gating becomes progressively stronger (harder) along the datapath. This configuration allows us to further balance wake-up overhead with leakage savings by exploiting the fact that logic circuits deep in the datapath have higher wakeup margin and hence can be strongly gated. Simulations show that multiple sleep mode capability provides an extra 17% reduction in overall leakage compared to traditional single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit.

Statistical analysis of SRAM cell stability

The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. We provide a theoretical framework for characterizing the DC noise margin of a memory cell and develop models for estimating the cell failure probabilities during read and write operations. The proposed models are verified against extensive Monte-Carlo simulations and are shown to match well over the entire range of the distributions well beyond the 3-sigma extremes

Power Gating with Multiple Sleep Modes

This paper describes a power gating technique with multiple sleep modes where each mode represents a trade-off between wake-up overhead and leakage savings. We show that high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. Our simulations and data traces show that multiple sleep mode capability provides an extra 17% reduction in overall leakage as compared to single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit

Modeling and analysis of crosstalk noise in coupled RLC interconnects

At current operating frequencies, inductive-coupling effects can be significant and should be included for accurate crosstalk-noise analysis. In this paper, an analytical framework to model crosstalk noise in coupled RLC interconnects is presented. The proposed model is based on transmission-line theory and captures high-frequency effects in on-chip interconnects. The new model is generic in nature and can be applied to asymmetric driver-and-line configurations for aggressor and victim wires. The model is compared against SPICE simulations and is shown to capture both the waveform shape and peak noise accurately. Over a large set of random test cases, the average error in noise-peak estimation is approximately 6.5%. A key feature of the new model is that its derivation and form enables physical insight into the total coupling-noise-waveform shape and its dependence on relevant physical-design parameters. Due to its simplicity and physical nature, the proposed model can be applied to investigate the impact of various physical-design optimizations (e.g., wire sizing and spacing, shield insertion) on total RLC coupled noise. The effectiveness of various existing noise-reduction techniques in the presence of mutual-inductance coupling is studied here. The obtained results indicate that common (capacitive) noise-avoidance techniques can behave quite differently when both capacitive and inductive coupling are considered together.

A Test Structure for Characterizing Local Device Mismatches

We present a test structure for statistical characterization of local device mismatches. The structure contains densely populated SRAM devices arranged in an addressable manner. Measurements on a test chip fabricated in an advanced 65 nm process show little spatial correlation. We vary the nominal threshold voltage of the devices by changing the threshold-adjust implantations and observe that the ratio of standard deviation to mean gets worse with threshold scaling. The large variations observed in the extracted threshold voltage statistics indicate that the random doping fluctuation is the likely reason behind mismatch in the adjacent devices

The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies

The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. First, we develop a theoretical framework for characterizing the dc noise margin of a memory cell. The framework is based on the concept that an SRAM cell is on the verge of instability when the gain across the loop formed by the cross-coupled inverters in the cell is unity. The noise margin criteria developed in this manner can be used to verify a cell stability in the presence of arbitrary DC noise offsets at the two storage nodes in the cell. We also develop metrics for estimating the cell stability during read and write operations and verify these models by extensive Monte Carlo simulations in a 65-nm CMOS process. Our results show that the proposed robustness metrics can be used to estimate cell failure probabilities in an efficient and accurate manner.

Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance

Increasing levels of process variation in current technologies have a major impact on power and performance, and result in parametric yield loss. In this work we develop an efficient gate-level approach to accurately estimate the parametric yield defined by leakage power and delay constraints, by finding the joint probability distribution function (jpdf) for delay and leakage power. We consider inter-die variations as well as intra-die variations with correlated and random components. The correlation between power and performance arise due to their dependence on common process parameters and is shown to have a significant impact on yield in high-frequency bins. We also propose a method to estimate parametric yield given the power/delay jpdf that is much faster than numerical integration with good accuracy. The proposed approach is implemented and compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%.

A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS

A 32 kb subarray demonstrates practical implementation of a 65 nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows single-supply operation down to 0.41 V at 295 MHz without dynamic voltage techniques. Despite a larger cell, array area is competitive with 6T-SRAM due to higher array efficiency. With an LSDL decoder, a gated diode sense amplifier, and design tradeoffs enabled by the 8 T cell, 5.3 GHz operation at 1.2 V is achieved.

Compensating non-optical effects using electrically driven optical proximity correction

Chip performance and yield are increasingly limited by systematic and random variations introduced during wafer processing. Systematic variations are layout-dependent and can be broadly classified as optical or non-optical in nature. Optical effects have their origin in the lithography process including mask, RET, and resist. Non-optical effects are layout-dependent systematic variations which originate from processes other than lithography. Some examples of nonoptical effects are stress variations, well-proximity effect, spacer thickness variations and rapid thermal anneal (RTA) variations. Semiconductor scaling has led to an increase in the complexity and impact of such effects on circuit parameters. A novel technique for dataprep called electrically-driven optical proximity correction (ED-OPC) has been previously proposed which replaces the conventional OPC objective of minimization of edge placement error (EPE) with an electrical error related cost function. The introduction of electrical objectives into the OPC flow opens up the possibility of compensating for electrical variations which do not necessarily originate from the lithographic process. In this paper, we propose to utilize ED-OPC to compensate for optical as well as non-optical effects in order to mitigate circuit-limited variability and yield. We describe the impact of non-optical effects on circuit parameters such as threshold voltage and mobility. Given accurate models to predict variability of circuit parameters, we show how EDOPC can be leveraged to compensate circuit performance for matching designer intent. Compared to existing compensation techniques such as gate length biasing and metal fills, the primary advantage of using ED-OPC is that the process of fragmentation in OPC allows greater flexibility in tuning transistor properties. The benefits of using ED-OPC to compensate for non-optical effects can be observed in reduced guard-banding, leading to less conservative designs. In addition, results show a 4% average reduction in spread in timing in compensating for intra-die threshold voltage variability, which potentially translates to mitigation of circuit-limited yield.

Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization

Variation is a significant concern in nanometer-scale CMOS due to manufacturing equipment being pushed to fundamental limits, particularly in lithography. In this paper, we review recent work in coping with variation, through both improved analysis and optimization. We describe techniques based on integrated circuit manufacturing, circuit design strategies, and mathematics and statistics. We then go on to discuss trends in this area, and a future technology outlook with an eye towards circuit and CAD-solutions to growing levels of variation in underlying device technologies.