Frank O'Mahony

A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power with data rate. Low-power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low-noise offset-calibrated receivers.

Modeling and Analysis of High-Speed I/O Links

Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design.

A 47

A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. The circuitry and interconnect are co-designed to minimize power and area for a wide parallel interface. Power is reduced by amortizing clocking, minimizing the span of clock signals and pairing a low-swing transmitter driver with a sensitive receiver sampler. The active silicon area is compressed by 64% relative to the C4 bumps using on-chip transmission line routing. A dense, top-side package connector and bridge enable both high off-chip interconnect density and low overall power by reducing equalization and deskew requirements. The interface also demonstrates fast power management for the I/O circuits. The receiver power can be reduced by 93% during standby and an integrated wake-up timer indicates that all lanes return reliably to active mode in <;5 ns. The interface operates at 470 Gb/s with an aggregate bit error ratio better than 2 ×10-18 while consuming 1.4 mW/Gb/s and occupies 3.2 mm2 active silicon area.

\,\times\,

The performance of high-speed wireline data links depend crucially on the quality and precision of their clocking infrastructure. For future applications, such as microprocessor systems that require terabytes/s of aggregate bandwidth, signaling system designers will have to become even more aware of detailed clock design tradeoffs in order to jointly optimize I/O power, bandwidth, reliability, silicon area and testability. The goal of this tutorial is to assist I/O circuit and system designers in developing intuitive and practical understanding of I/O clocking tradeoffs at all levels of the link hierarchy from the circuit-level implementation to system-level architecture.

10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS

Future microprocessor platforms will require system-level optimization of the I/O to minimize cost and maximize aggregate bandwidth. Critical parameters such as silicon area, power, testability, and off-chip interconnect quality must be properly balanced to maximize the I/O performance versus cost ratio. For example, there is a fundamental tradeoff between clock quality and equalizer effectiveness [1]. Producing precision RX and TX clocks and a sensitive RX may impact the power and area of some circuits, but it could allow the use of simple, low-power linear equalizers to minimize the overall link power. Additionally, these equalizers will become much more effective by limiting near-end crosstalk and stubbed backplane (BP) via length. To demonstrate this system-level optimization effort, we have developed a 20Gb/s forwarded clock I/O system intended for a wide parallel link with small area and low power.

Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial

This paper describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2 Gb/s data rate with BER < 10-12 across 14 cm of PCB, and also an 8.0 Gb/s data rate through 4 cm of PCB. Designed in a 1.2 V, 90 nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6 GHz. The total area of each receiver is 0.0174 mm2, resulting in a measured power efficiency of 0.6 mW/Gb/s.

A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.

A general model for injection-locked LC oscillators (LC-ILOs) is presented that is valid for any tank quality factor and injection strength. Important properties of an ILO such as lock-range, phase shift, bandwidth and response to input jitter are described. An LC-ILO together with a half-rate data sampler is implemented as a forwarded-clock I/O receiver in 45-nm CMOS. A strongly-injected low-Q LC oscillator enables clock deskew across 1UI and rejects high-frequency clock jitter. The complete 27 Gb/s ILO-based data receiver has an overall power efficiency of 1.6 mW/Gb/s.

A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS

This paper describes a method for both filtering and deskewing a link clock using a differential injection-locked LC-DCO and demonstrates a forwarded-clock data receiver using this technique operating at 27 Gb/s.

Strong Injection Locking in Low-

A 10GHz clock generation and distribution network for an 8-channel 20Gb/s/channel data transmitter is demonstrated in a 90nm 1.2V CMOS process. Jitter due to power supply and device noise is minimized with an LC VCO and repeaterless clock network. The performance of the forwarded-clock link degrades by only 4% due to plusmn5% supply noise at the transmitter. The LC VCO achieves supply noise sensitivity of 200MHz/V (0.02%-frequency/1%-supply noise) and short-term (8-symbol) rms jitter of 100fs. The clock distribution network delay sensitivity to supply noise is 36ps/V. The total clocking power is 408mW

Q

High-speed CMOS microprocessor I/O has scaled aggressively over the past decade in terms of power and performance largely due to advances in equalization and clocking techniques. With future multi-core processors expected to require ≫1TB/s bandwidth and dramatically improved power efficiency, there has been some question as to whether electrical I/O will continue to satisfy chip-to-chip communication requirements over the next decade. In this paper, we show that electrical signaling has the power, performance, and density scaling potential to enable the next several generations of systems and applications. Circuit innovation is aggressively pushing link power efficiency toward 1–2mW/Gb/s while departures from legacy channels to include new topologies and materials can significantly improve the power/performance/density tradeoff. Statistical link-level design tools that allow designers to rapidly quantify high-level architecture tradeoffs will enable balanced link designs that co-optimize power, performance, and channel topology.