Mozhgan Mansuri

Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops

This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies (periods of less than 8x the delay of a fan-out-4 inverter (FO-4)) and faster frequency acquisition. Prototypes designed in 0.25-µm CMOS process exhibit operating frequencies of 1.25 GHz ( = 1/(8 ċ FO-4) ) and 1.5 GHz ( = 1/(6.7 ċ FO-4) ) for two techniques respectively whereas a conventional PFD operates < 1 GHz ( = 1/(10 ċ FO-4) ). The two proposed PFDs achieve a capture range of 1.7x and 1.2x the conventional design.

Jitter optimization based on phase-locked loop design parameters

A tunable PLL allows independent optimization of loop parameters. The effects of varying PLL parameters (damping factor and bandwidth) on timing jitter is derived analytically and verified experimentally.

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a wide range of operating frequencies. The design uses static CMOS inverters as a building block of the voltage-controlled oscillator and clock buffering. To reduce supply-induced jitter, programmable circuits with opposite sensitivity compensate for the delay variations. Both elements have supply-induced delay sensitivity of /spl les/0.1%-delay/1%-V/sub DD/. The design is fabricated in 0.25-/spl mu/m CMOS technology and consumes 10mW from a 2.5-V supply. The experimental results verify that the proposed methods significantly improve the jitter.

A low-power low-jitter adaptive-bandwidth PLL and clock buffer

A multi-context programmable on-chip communication network is implemented using a matrix of Flash-EEPROM pass-transistor switches (FPT) in a 0.18/spl mu/m technology. The prototype 8-context, 8/spl times/8 64b crossbar includes 576k FPT and >8k bi-directional tristate repeaters in an area of 1.38mm/sup 2/. Based on 2/spl times/2 building blocks, wave pipelining and elastic interconnect, data is transferred at 6.4Gb/s per channel, with independent clocks at both ends.

A 27-mW 3.6-Gb/s I/O transceiver

This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300 uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.

Methodology for on-chip adaptive jitter minimization in phase-locked loops

This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 /spl mu/m CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter.

An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements

This paper presents a scalable all-digital power supply noise analyzer with 20GHz sampling bandwidth and 1mV resolution implemented in 32nm CMOS. This averaging-based analyzer measures power supply noise in both the equivalent-time and frequency domain with low-resolution VCO-based samplers. For frequency-domain measurements, it uses digital random phase-noise accumulation to remove correlation between the power supply noise and sampling clocks. In addition, the equivalent-time current step response is measured on-die to characterize the frequency-domain impedance of the power delivery network.