Frank Schmiedle

Exact routing with search space reduction

The layout problem in VLSI-design can be broken up into the subtasks partitioning, floorplanning, placement, and routing. In the routing phase, a large number of connections between the blocks and cells have to be established, while intersections lead to short circuits and, therefore, have to be avoided. We present an approach for exact routing of multiterminal nets that complements traditional routing techniques. It is particularly well suited for an application to dense problem instances and the completion of routing in subregions, which turn out to be difficult for routing tools based on heuristic methods. The exact router proposed uses symbolic methods, i.e., MDDs (multivalued decision diagrams) for representation of the routing space. For the necessary computations of routing solutions, we profit considerably from the efficient basic operations on MDDs. All possible solutions to the routing problem are represented by one single MDD and, once this MDD is given, routability can be decided within constant time. To reduce the search space of possible routing solutions, so-called forced cells are computed. Experimental results are given to show the feasibility and the practicability of the approach.

Heuristic Learning Based on Genetic Programming

In this paper we present an approach to learning heuristics based on Genetic Programming (GP) which can be applied to problems in the VLSI CAD area. GP is used to develop a heuristic that is applied to the problem instance instead of directly solving the problem by application of GP. The GP-based heuristic learning method is applied to one concrete field from the area of VLSI CAD, i.e. minimization of Binary Decision Diagrams (BDDs). Experimental results are given in order to demonstrate that the GP-based method leads to high quality results that outperform previous methods while the run-times of the resulting heuristics do not increase. Furthermore, we show that by clever adjustment of parameters, further improvements such as the saving of about 50% of the run-time for the learning phase can be achieved.

Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics

Among many other applications, evolutionary methods have been used to develop heuristics for several optimization problems in VLSI CAD in recent years. Although learning is performed according to a set of training benchmarks, it is most important to generate heuristics that have a good generalization behaviour and hence are well suited to be applied to unknown examples. Besides large runtimes for learning, the major drawback of these approaches is that they are very sensitive to a variety of parameters for the learning process.In this paper, we study the impact of different parameters, like e.g. stopping conditions, on the quality of the results for learning heuristics for BDD minimization. If learning takes too long, the developed heuristics become too specific for the set of training examples and in that case results of application to unknown problem instances deteriorate. It will be demonstrated here that runtime can be saved while even improving the generalization behaviour of the heuristics.

Selection of efficient re-ordering heuristics for MDD construction

Multi-valued decision diagrams (MDDs) are a generalization of binary decision diagrams (BDDs). They are suitable for several applications in synthesis and verification of integrated circuits since often, functions with multi-valued input variables can be represented efficiently by MDDs. Their sizes counted in number of nodes vary from linear to exponential dependent on the variable ordering used. Therefore sifting, i.e. dynamic variable re-ordering, has to be applied frequently while an MDD is built in order to keep the number of nodes needed during the process small. Often most of the runtime for MDD construction is spent for sifting. We present a new method that speeds up MDD construction and also reduces memory consumption. It is based on the selection of re-ordering heuristics dependent on the history of the construction process. Success of previous re-ordering steps as well as the frequency of sifting calls in the past are used to determine a variation of sifting that is applied next. Experimental results are given to demonstrate that runtimes and memory consumption can be reduced by 30% on average when the proposed selection methods are used during MDD construction.