Frank W. Angelotti

Modeling for structured system interconnect test

With the acceptance of test standards such as IEEE 1149.1, the potential for structured methods for system test is growing rapidly. In particular, interconnect testing based on standardized boundary scan structures will be an important component of a future structured system test methodology. A strategy based on building an interconnect topology model of the system under test and using that model to generate interconnect test patterns at test time provides for a level of system test coverage that is difficult or impossible to obtain from methods based on static stored test patterns. This paper discusses the problem of dynamically generating a model of system interconnect topology for use in structured interconnect test generation and analysis. A solution for the most general case is given and some simple system design for test rules that greatly simplify the process are proposed. Several additional solutions which explore some potential trade-offs are discussed. A practical algorithm that requires minimal storage and reasonable computation is proposed.

SCITT: Bringing DRAMs Into the Test Fold

dously successful in addressing the problem of component, board and system level interconnect testing. The standard is widely embraced by the semiconductor industry and virtually any logic component can be found in an 1149.1 compliant version. The glaring exception is DRAM devices. This prevents a sound, structured and standardized interconnect test methodology from being applied to a significant portion of a modern system, namely the memory interface. The time is clearly at hand for the development of a standard for structured interconnect test that is feasible and acceptable for DRAM devices. Such a standard would ideally: 1) be usable at different levels of the packaging/manufacturing process (i.e. chip package, module, system); 2) provide effective, adequate isolation and diagnostic information; 3) be low cost and low overhead so it will be embraced by the industry; 4) not preclude innovation in the future. The current SCITT proposal is an admirable attempt at addressing these multiple and potentially conflicting criteria. However we believe that several modifications to SCITT would ultimately lead to a more flexible and usable standard.

Generating interconnect models from prototype hardware

With widespread acceptance of the IEEE 1149.1 standard, structured interconnect testing has become extremely important at the MCM, PWB and system levels. In the conventional paradigm, an interconnect topology model of the system under test is extracted from design information. From this model, interconnect test patterns can be generated by means of well understood algorithms. We demonstrate a new approach whereby the interconnect topology model is extracted by directly probing a hardware prototype of the system under test. This Golden Model can then be used to generate interconnect tests for other systems whose interconnect topology matches that of the prototype. Algorithms for this Golden Model extraction are presented and analyzed, empirical results are given, and the benefits and drawbacks of the approach are discussed.