Fred J. Meyer

Testing configurable LUT-based FPGA's

We present a new technique for testing field programmable gate arrays (FPGAs) based on look-up tables (LUTs). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUTs, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (l-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.

Multiple fault detection in logic resources of FPGAs

An approach is proposed to detect multiple faults in FPGAs. The approach exploits the testability of the AND tree and OR tree with the configurability and programmability of SRAM-based FPGAs. The proposed AND tree- and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test generation for only a single CLB is required as the AND/OR approach scales to larger FPGAs. CLB test generation can assume any desired fault model. Any number of faulty CLBs in the chip can be detected.

A XOR-tree based technique for constant testability of configurable FPGAs

This paper presents a novel approach for testing and diagnosing configurable field programmable gate arrays (FPGAs). The proposed approach is row-based and uses a two-session procedure. The approach arranges some logic blocks to be programmed as XOR-tree (or chain, or cascade) in the first session. The XOR-tree is effectively used as test vehicle for observability. The roles of the CLBs are inverted in the second session. It is shown that the proposed testing arrangement requires a number of tests independent of the number of CLBs in the FPGA (i.e. C-testability is accomplished). Routing is kept local, and compatibility for a CAD implementation is also accomplished.

Measuring the timing jitter of ATE in the frequency domain

The objective of this paper is to provide a framework by which jitter, in the output signals of a test-head board in an automatic test equipment (ATE), can be measured. In this paper, jitter phenomena caused by radiated electromagnetic interference (EMI) noise are considered. EMI noise is mainly present in the test head of an ATE as result of the activity of the dc-dc converters. An analysis has been pursued to establish the areas of the test-head board that are most sensitive to EMI noise. The most sensitive part of the test-head board has been found to occur in the loop filter of the phase-locked loop (PLL) that is used to obtain a high-frequency clock for the timing generator (TG). Different H-fields are then externally applied to the loop filter to verify the behavior of the output signal in terms of rms jitter. A frequency-domain methodology has been employed for the rms-jitter measurements. The rms-jitter variation for the radiated EMI magnitude and frequency has been characterized. Also, the orientation of the external H-field source has been investigated with respect to the target board and its effects on the measured rms jitter. For measuring the jitter, an interface circuitry has been designed on an adapter board to circumvent ground noise and connectivity problems arising from the test-head environment.

Reconfiguration of one-time programmable FPGAs with faulty logic resources

A comprehensive approach is given to reconfigure field programmable gate arrays (FPGAs) with faults in the logic resources. Reconfiguration consists of a reassignment of the cells that takes into account the one-time programmable nature of the chip resources. The method alters neither the FPGA nor the fault-free design; so the effectiveness of the reassignment depends on the efficient use of routing resources in the fault-free design. Under a generalized architecture, the spare routing resources needed are obtained to bypass each faulty cell and reassign its functions to a spare (unused) cell. If every channel has as many spare trades as half the number of logic cell inputs and outputs, then any single faulty cell can be reassigned, thus yielding a successful chip reconfiguration. The proposed reassignment algorithm has an efficient execution, so it can be run while chips are programmed and tested on an assembly line. The number of calls to the routing software is at worst quadratic in the number of faulty cells, provided no backtracking is needed in the reassignment. Under some randomness assumptions, the average number of calls to the routing software is linear in the number of faulty cells. The proposed method is analyzed with benchmark circuits and simulation results are presented.

Testing of programmable logic devices (PLD) with faulty resources

This paper presents a combined approach for testing logic and routing resources in programmable logic devices (PLDs). The proposed approach is based on configuring the PLD using different arrangements such as built-in self-test schemes (for example, a parity chain) and one-dimensional arrays (with and without common inputs). It is proved that the proposed approach achieves 100% fault coverage under a fault model consisting of a single fault in the logic resources and active routing devices, or multiple faults in the interconnection channels and input/output lines.

Maximal diagnosis of interconnects of random access memories

This paper presents an approach for the maximal diagnosis of all faults (stuck-at, open and short) in the interconnect of a random access memory (RAM); the interconnect includes data and address lines. This approach accomplishes maximal diagnosis under a complex model in which the lines in the interconnect of the RAM are involved in multiple faults simultaneously. The proposed algorithm (referred to as the Improved Maximal Diagnosis Algorithm, or IMDA) requires max{n,m-I}+n+3 WRITE and max{n,m}+2n READ, where n is the number of address lines and m is the number of data lines.

Design verification of FPGA implementations

This approach uses the criterion of equivalent classes to establish the equivalence between two circuits and designs. Combining simulation and automatic test pattern generation, it exploits similarities among designs to assess logical equivalence quickly and reliably.

Fault detection and diagnosis of interconnects of random access memories

This paper presents two new approaches for testing interconnects of random access memories (RAM). Tire first algorithm is referred to as the Adaptive Diagnosis Algorithm (ADA), while the second algorithm is referred to as the Consecutive Diagnosis Algorithm (CDA). Initially, it is shown that the diagnosis of the address lines is the most difficult step in interconnect testing of memories as the diagnosis of faults in data lines can be resolved easily. The execution of ADA is such that the diagnosis of the address lines is performed sequentially (i.e. on a line by line basis), while enforcing the conditions by which it is possible to differentiate for each line a stuck-at fault from a short. This is determined by the operations as for diagnosis a short requires an additional READ compared with a suck-at fault. A different condition in the generation of the overall sequence is utilized in CDA; by using different test patterns for the address lines, a relation can be assessed between consecutive READ operations.

Adaptive approaches for fault detection and diagnosis of interconnects of random access memories

This paper presents three new approaches for testing interconnects of random access memories (RAM). These algorithms are referred to as the Adaptive Diagnosis Algorithm (ADA), the Consecutive Diagnosis Algorithm (CDA) and the Adaptive Diagnosis Algorithm with Repair (ADAR). For diagnosis, ADA requires max{n+1,p} WRITE and max{n,p} READ, while CDA requires max{n+1,p} WRITE and n+p READ, where n(m) is the number of address (data) lines and p is the least integer such that C/sub p/2//sup p//spl ges/m. A different scenario referred to as maximal diagnosis, is considered next. Maximal diagnosis refers as the full diagnosis of all detectable and diagnosable faults in the interconnect with no repair. ADAR utilizes various test iterations to achieve maximal diagnosis; between each pair of iterations, repair of the diagnosed lines takes place. In ADAR, two repair and three test iterations are required. ADAR requires a total of 2n+m+3 WRITE and 3n+m+1 READ.