Xiao-Tao Chen

Testing configurable LUT-based FPGA's

We present a new technique for testing field programmable gate arrays (FPGAs) based on look-up tables (LUTs). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUTs, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (l-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.

On the diagnosis of programmable interconnect systems: Theory and application

This paper considers the diagnosis of field programmable interconnect systems (FPIS) in which programmable grids made of switches are included. For this type of interconnects, the number of times the grid must be programmed and the programming sequence of the switches an two of the most important figures of merit for full diagnosis (defection and location with no aliasing and confounding). A hierarchical approach to diagnosis is proposed and fully characterized. The application of this technique to commercially available FPIS such as FPGAs, is discussed. It is shown that the proposed diagnostic technique can be applied to the general purpose interconnect of the FPGAs in the 3000 family by Xilinx.

Reconfiguration of one-time programmable FPGAs with faulty logic resources

A comprehensive approach is given to reconfigure field programmable gate arrays (FPGAs) with faults in the logic resources. Reconfiguration consists of a reassignment of the cells that takes into account the one-time programmable nature of the chip resources. The method alters neither the FPGA nor the fault-free design; so the effectiveness of the reassignment depends on the efficient use of routing resources in the fault-free design. Under a generalized architecture, the spare routing resources needed are obtained to bypass each faulty cell and reassign its functions to a spare (unused) cell. If every channel has as many spare trades as half the number of logic cell inputs and outputs, then any single faulty cell can be reassigned, thus yielding a successful chip reconfiguration. The proposed reassignment algorithm has an efficient execution, so it can be run while chips are programmed and tested on an assembly line. The number of calls to the routing software is at worst quadratic in the number of faulty cells, provided no backtracking is needed in the reassignment. Under some randomness assumptions, the average number of calls to the routing software is linear in the number of faulty cells. The proposed method is analyzed with benchmark circuits and simulation results are presented.

A coloring approach to the structural diagnosis of interconnects

This paper presents a new approach for diagnosing stuck-at and short faults in interconnects whose layouts are known. This structural approach exploits different graph coloring and coding techniques to generate a test set with no aliasing and confounding. The conditions for aliasing and confounding are analyzed with respect to the size and number of the shorts in the fault set. The characteristics of unbalanced/balanced codes for encoding the colors in the vector generation process for interconnect diagnosis are discussed and proved using a novel algebra. An algorithm for diagnosis is then presented.

Layout-driven detection of bridge faults in interconnects

This paper presents a new approach to fault detection of interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults by a novel weighted graph approach. This graph is then analyzed to appropriately schedule the order of test compaction and execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weights of the new adjacency graph as figure of merit. The advantage of the proposed approach is that on average, early detection of faults is possible using a number of tests significantly smaller than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still requiring a small number of vectors.

Design verification of FPGA implementations

This approach uses the criterion of equivalent classes to establish the equivalence between two circuits and designs. Combining simulation and automatic test pattern generation, it exploits similarities among designs to assess logical equivalence quickly and reliably.

Structural diagnosis of interconnects by coloring

This paper presents a new approach for diagnosing shorts in interconnects in which the adjacencies between nets are known. This structural approach exploits different graph coloring techniques to generate a test set with no aliasing and confounding, i.e., full diagnosis (detection and location) is accomplished. Initially, a simple coloring approach based on a greedy condition of the adjacency graph is proposed for fault detection. Then, the conditions for aliasing and confounding are analyzed with respect to the sizes of the possible shorts. These results are used to generate new colors using a process called color mixing. Color mixing guarantees that additional tests, required in order to avoid aliasing/confounding, will use appropriate codes. The characteristics of unbalanced/balanced codes for encoding the colors in the vector-generation process of interconnect diagnosis are discussed and are proved to yield full diagnosis using a novel method. An algorithm for full diagnosis is then presented; this algorithm has an execution complexity of <italic>O</italic>(<italic>max</italic>{<italic>N</italic><supscrpt>2</supscrpt>, <italic>N</italic>×<italic>D</italic><supscrpt>3</supscrpt>}) where <italic>N</italic> is the number of nets and <italic>D</italic> is the maximum degree of the nodes in the adjacency graph. Simulation results show that the proposed approach requires a smaller number of test vectors than previous approaches.

Fault tolerance of one-time programmable FPGAs with faulty routing resources

This paper presents a novel approach for fault tolerance of one-time programmable FPGAs by reassignment of routing resouces. As the underlying problem is NP-complete, a greedy algorithm is proposed to provide rapid, but suboptimal solutions. Due to the one-time programmable characteristic of the switches (commonly referred to as antifuses), only unused (fault-free) routing resources must be utilized for reassignment in a chip with a faulty interconnect. We specifically investigate whether reassignment could be accomplished without changing the global routing of any connections. A RC-tree model for the net delay is also presented; delay bounds are established to fully quantify the degradation due to the reassignment. Extensive simulation results are provided.

Novel approaches for fault detection in two-dimensional combinational arrays

This paper presents new approaches for the constant (C)-testability of orthogonal (two-dimensional) arrays of combinational cells. A novel testability condition referred to as CO-testability is introduced: a testing approach for CO-testability is fully characterized based on adding states to the table of a cell. A second approach is also proposed. this approach is based on adding a variable number of additional states to a cell with a known table. This approach requires at most (m+k+/spl alpha/)(n+k+/spl alpha/)( m/k+1)(n/k+1) tests, where m and n are the number of states in the two dimensions of signal flow, /spl alpha/=1(0) if (partial) fail observability is applicable to the state table and k is the variable number of additional states per direction (2/spl les/k/spl les/m.n). As an example, the proposed approaches have been applied to a two-dimensional array for maximum/minimum comparison.

Accurate communication models for task scheduling in multicomputers

Models for computations and message-passing communications are very important for scheduling applications onto multicomputer systems and estimating the parallel execution time. This paper presents new models for communication, scheduling and estimating the execution time. In the proposed models, it is assumed that each processor in the multicomputer system has a router. The processor can only receive data from and send data to the router sequentially while the router can receive data from and send data to the routers of other processors in parallel. The execution time of a given application on a given machine can be then accurately estimated by using the proposed models. The input parameters to the proposed models are determined by measuring some parameters experimentally. Experimental results on the nCUBE2 machine are given to show the correctness of the proposed models.