Wei Kang Huang

Testing configurable LUT-based FPGA's

We present a new technique for testing field programmable gate arrays (FPGAs) based on look-up tables (LUTs). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUTs, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (l-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.

Approaches for the repair of VLSI/WSI RRAMs by row/column deletion

The authors present two approaches for the repair of large random access memory (RAM) in which redundant rows and columns have been added as spares. These devices, referred to as redundant RAMs, are repaired to achieve acceptable yields at production time. The first approach, namely, the faulty-line-covering technique, is a refinement of the fault-driven approach. This approach finds the optimal repair-solution within a smaller number of iterations than the fault-driven algorithm. Simulation results show that the faulty-line-covering technique will execute much faster under all fault distributions. The second approach uses a heuristic criterion in the generation of the repair-solution. This heuristic criterion permits a very fast repair. The criterion is based on the calculation of efficient coefficients for the rows and columns of the memory. Two techniques for coefficient selection are proposed.<<ETX>>

A new diagnosis approach for short faults in interconnects

Existing one-step diagnosis approaches for faults in interconnects either yield a long test sequence, or use a non-generalized procedure to generate a shorter test sequence. We propose a new diagnosis approach for short faults in interconnects. The pin-adjacency fault model is assumed. By using a divide-and-conquer strategy, our approach can generate a very compact test vector sequence which can diagnose an unrestricted number of short faults. Our experiments for three benchmarks as well as large random interconnects (up to 50,000 nets) show that our approach can achieve more than 50% savings in the length of the generated test sequence. This can significantly save the diagnosis cost for boundary-scan testing. An adaptive diagnosis approach is further proposed to dynamically truncate the originally generated test sequence based on the current information of faulty nets. The performance of our adaptive approach in terms of the on-line test generation time and the resulting test sequence length is better than for existing adaptive diagnosis approaches when the fault rate is not very small, such as in a new product line. If a low complexity for the ATE is of major importance, then the proposed one-step approach is the best choice.<<ETX>>

An approach for detecting multiple faulty FPGA logic blocks

An approach is proposed to test FPGA logic blocks, including part of the configuration memories used to control them. The proposed AND tree and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test generation for only a single logic block is sufficient. We do not assume any particular fault model. Any number of faulty blocks in the chip can be detected. Members of the Xilinx XC3000, XC4000, and XC5200 families were studied. The proposed AND/OR approach was found to reduce the number of FPGA reprogrammings needed for testing by up to a factor of seven versus direct methods of multiple faulty block detection.

Minimizing the number of programming steps for diagnosis of interconnect faults in FPGAs

This paper presents a procedure to diagnose single faults in SRAM based FPGAs. The procedure is nonadaptive and requires six programming steps to give the exact position and type of any single fault in a FPGA. It is proved that the number of programming steps required for the procedure is minimal for a non-adaptive procedure with the given interconnect model.

Diagnosing single faults for interconnects in SRAM based FPGAs

This paper presents a method to diagnose faults in FPGA interconnection resources. A single fault model is given. Under the given model, a diagnosing method is proposed. At most five programming steps in the proposed method is required if adaptive testing scheme is used. For non-adaptive test, eight programming steps is required to diagnose all the possible faults under the given single fault model. The accuracy of the fault diagnosing is one segment for a segment stuck-at or stuck-open fault, a segment pair for a bridge fault, a switch for switch stuck-on or stuck-off fault.

Testing and testable designs for one-time programmable FPGAs

We present a methodology for production-time testing of one-time programmable field programmable gate arrays (FPGAs) such as those manufactured by Actel. The methodological principles are based on connecting the uncommitted modules (sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays, similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions for constant testability (C testability). Two design approaches are proposed. Features such as testing time and hardware requirements (measured by the number of cycles and additional transistors and primary input-output pins) are analyzed. We show that the proposed designs require considerably less testing time than a previous technique based on scan. The proposed approaches require 8+n/sub f/ vectors for testing the Actel FPGAs, where n/sub f/ is the number of flip-flops in a row. Hardware overhead for the testing circuitry is also analyzed.

Fault detection in a tristate system environment

We present a novel approach for detecting faults in tristate system environments-e.g., in multiple board systems. These environments are made of an interconnect and drivers/receivers with tristate features. We present a comprehensive fault model that includes faults in terminals (drivers/receivers) and nets. Under this fault model, physical faults (stuck-at and short), as well as functional faults (dominance, permanently enabled or permanently disabled driver modes), are taken into account. We show that, for a single net with L drivers, 2L tests are necessary and sufficient for fault detection. This is independent of the number of receivers. We extend this result to a system environment with N nets and where K is the maximal number of drivers for a net. Under the proposed fault model, any number of faults of any type can be detected in a system environment using any types that can be detected in a system environment using max (2K, P) tests, where P is the minimal integer that satisfies C/sub /2//sup P//spl ges/N. If only the traditional (wired-AND or wired-OR) model is assumed, then the test set required for fault detection can be further reduced. We provide simulation results and show that the proposed approach outperforms previous methods found in the technical literature.

Using virtual links for reliable information retrieval across point-to-point networks

The problem of establishing reliable communication across point-to-point networks is addressed. Several protocols are given, using node-disjoint paths to implement a set of independent virtual links (u-links) between each node pair. The u-links can be used to establish communication between the node pair provided the number and type of failures in the network are limited. Failed devices are classified by whether they are benign (delay and omission faults) or are malicious (not benign). The use of u-links is demonstrated with a protocol for remote information retrieval. With b benign and m malicious faults, retrieval can always be achieved if the graph connectivity exceeds b+2 m. This bound is tight. The authors give a flexible retrieval protocol; it analyzes the responses received thus far, and computes a minimum and maximum number of u-links to send (additional) retrieval requests. Maximal requests guarantee completion of the protocol upon their timeout. With minimal requests, protocol completion is barely possible with no further requests. u-links are extended so that they bounce requests when there is no response, which strengthens the retrieval protocol.