Erwin Jacobs

A memory-based high-speed digital delay line with a large adjustable length

The digital delay line concept is based on a dynamic three-transistor cell memory, with pointer access and offers high operating frequency, large maximum length, and low power dissipation. The adjustable delay requires only a small overhead for control logic. An experimental chip with 60 K transistors, which utilizes this concept, has been built in a 1.5- mu m CMOS technology. The adjustable delay ranges from 1 to 4096 clock cycles for a 4-bit-wide data word. Correct operation of the chip has been verified for clock frequencies in the range of 3 kHz to 30 MHz. Therefore the circuit is suitable for audio as well as video applications. >

Comparison of latch-up in p- and n-well CMOS circuits

The latch-up hardness of p- and n-well CMOS concepts is compared for processes with and without epitaxial layer using electrical and laser-scanning measurements as well as theoretical calculations. It is shown that latch-up hardness does not primarily depend on the parasitic bipolar gain products, which are different for the two concepts, but rather on the shunt resistors in the well and in the substrate. This leads to equal latch-up hardness for n- and p-well concepts without epitaxy. With epitaxy latch-up hardness is strongly increased and is in the case of a p-well by a factor of 5 higher compared with the n-well concept. This is due to the enhanced diffusion of Boron from the p+-substrate in the epitaxial layer.

Charge storage by irradiation with UV light in non-biased MNOS structures

Charge storage in non-biased MNOS (Metal-Nitride-Oxide-Semiconductor) structures effected by irradiation with UV light has been investigated. The electrons generated by internal photoemission at the Si surface are trapped at the SiO2Si3N4-interface and inside the Si3N4. The resulting charge storage in the insulator can be determined by capacitance technique. The observed positive voltage shift in C-V-characteristics depends on photon energy as well as on radiant exposure. The charge storage occurs in three stpes which can be related to various types of traps. The charged structure can partially be discharged by irradiation with light of less energy than needed for the storage process.

Method for manufacturing VLSI complementary MOS field effect transistor circuits in silicon gate technology

Complementary MOS field effect transistor circuits are produced in silicon gate technology, with the method steps up to the structuring of the gate electrode being executed in a known manner. Both source/drain implantations (FIG. 3, 8 and FIG. 5, 10) occur with only one mask (7a). This mask (7a), which is composed of silicon nitride, is utilized for the source/drain implantation 8 of the n-channel transistors (9). The source/drain implantation (10) for the p-channel transistors (11) occurs without a mask and the oxide layer thickness, d6, over the source/drain regions of the n-channel transistors (9) functions as a masking layer. An advantage of this process sequence is that switched capacitor structures (FIG. 6, 5b, 12) can be simultaneously produced whereby the oxide layer thickness, d4, over the polysilicon-1 level (5a, 5b) determines the thickness of the insulating layer, dcox, of the capacitor structures (5b, 12). This technique is useful for manufacturing VLSI CMOS circuits in VLSI technology with and without switched capacitors.

Optically induced charge storage in ion implanted SiO2

Abstract Charge storage in MOS structures with an ion implanted oxide layer has been investigated. The electrons generated by internal photoemission are captured in SiO2 traps which are created by the implantation of Kr+ and N+ ions at energies of 50–290 keV and a fluence up to 1014 cm−2. The charge storage results in a voltage shift of the high frequency C-V-curve. The dependence of electron storage on exposure time has been measured and compared with approximative calculations. The discharge of traps occurs by heating treatment and hints at the existence of deep oxide traps combined with structural lattice defects.

n-Channel Si-gate process for MNOS EEPROM transistors

Abstract An n -channel Si-gate process has been developed to fabricate MNOS EEPROM transistors and fast logic circuits on one chip. The technology proposed involves low thermal oxidation temperatures ≤900° C after nitride deposition, two LOCOS process steps and application of self-aligned overlapped poly-Si contacts. The MNOS memory transistors obtained have been programmed by ±25 V pulses with a write time of t w = 10 ms and an erase time of t e = 100 ms. The retention data have been found to be dependent on nitride thickness and threshold voltage shift, but independent of channel length and channel doping. For devices with a nitride thickness of 30.5 nm the short-term decay rate of 0.6 V/(decade of time) has been determined. Endurance testing using up to 10 7 pulses of ±25 V, 100 μs corresponding to approx. 10 4 write/erase cycles showed no time dependence for the decay rate over the time of 10 5 min in which retention measurements were made.

Reduced n + /p + -spacing with high latchup hardness in self-aligned double well CMOS technology

Latchup in CMOS circuit with an epitaxial layer originates from short channel effects of the parasitic field oxide transistors and from voltage drops on shunt resistances. The short channel behaviour of the field oxide transistors was improved by reducing the p-well depth and modifying the local oxidation step for the well generation. By laser scanning microscope it is shown that for the conventional well latchup firing occurs at the bulges of the well boundary. Using the shallow well the charge compensated region at the well boundary and thereby the latchup sensitive bulges are eliminated. With shallow p-well the shunt resistances are reduced by diminished out-diffusion of the heavily doped n+-substrate and by feasible use of a thinner epi-layer. These measures enable to reduce the critical n+/p+-spacing of adjacent n-and p-channel transistors from 12 µm to 6µm without loosing latchup hardness.

Electron mobility in Si-MOSFETs with an additional implanted channel

Abstract A narrow layer of As donors was implanted near the Si-SiO2 interface of n-channel Si MOSFETs/ The drain current flows partially in the implanted channel where the electrons approach bulk mobilities. Gate field dependent measurements of the Hall mobility and the transistor action are reported for 300 and 4.2 K.

N- and p-well process compatibility in a 1µm-CMOS technology

A 1 µm CMOS concept for 5 V supply-voltage with 22 nm gate oxide and a pure TaSi2gate is presented which allows to realize a n-well- and a p-well-process with widely compatible process flow. Starting in either case from 20 Ωcm epitaxial material on 0.02 Ωcm substrate the process uses equal well depths and identical low well dopant concentrations. Charge carrier mobilities have been found identical in both process concepts. N-channel low-level breakdown voltage is independent of the process concept used. Also independent of the well type the specific junction capacitances inside the well are nearly identical, outside the well typically different. Using ring oscillators with Leff=1.2 µm minimum propagation delays of 120ps for the p-well process and 190ps for the n-well process have been measured.

Short channel erase in n-channel Si-gate MNOS EEPROM transistors

A unipolar method of erasing MNOS EEPROM transistors with short channel lengths by reverse-biasing of source and drain with gate and substrate grounded is described for n-channel Si-gate transistors. With pulse conditions kept constant, the threshold voltage shift caused by short channel erase (SCE) depends strongly on channel length and nitride thickness of the transistors. At effective channel lengths < 0.4 μm, SCE voltages VSCE < 20 V are sufficient to cause a shift in the threshold voltage comparable to the value obtained with 25 V pulses using the conventional erase method and both voltage polarities. SCE voltage measurements at varied temperatures show that the results are in agreement with the model conception of the avalanche punch-through erase (APTE) mode. The retention data have been found regardless of the SCE treatment. Endurance has been investigated by multiple cycling of MNOS transistors using up to 107 pulses of 25 V, 100 μs. The effective window width did not change, but the transconductance was found to decrease slightly with cycle number.