Fred S. Lee

A 2.5 nJ/bit 0.65 V Pulsed UWB Receiver in 90 nm CMOS

A noncoherent 0-16.7 Mb/s ultra-wideband (UWB) receiver using 3-5 GHz subbanded pulse-position modulation (PPM) signaling is implemented in a 90 nm CMOS process. The RF and mixed-signal baseband circuits operate at 0.65 V and 0.5 V, respectively. Using duty-cycling, adjustable bandpass filters, and a relative-compare baseband, the receiver achieves 2.5 nJ/bit at 10-3 BER with -99 dBm best case sensitivity at 100 kb/s. The energy efficiency is maintained across three orders of magnitude in data rate. For data rates less than 10 kb/s, leakage power dominates energy/bit.

A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB Receiver in 90nm CMOS

A non-coherent 0-to-16Mb/s UWB receiver using 3-to-5GHz subbanded PPM signaling is implemented in a 90nm CMOS process. The RF and mixed-signal baseband circuits operate at 0.65V. Using duty-cycling, adjustable BPFs, and an energy-aware baseband, the receiver achieves 2.5nJ/b and 10-3 BER with -95dBm sensitivity at 100kb/s.

System design considerations for ultra-wideband communication

This article discusses issues associated with high-data-rate pulsed ultra-wideband system design, including the baseband processing, transmitter, antenna, receiver, and analog-to-digital conversion. A modular platform is presented that can be used for developing system specifications and prototyping designs. This prototype modulates data with binary phase shift keyed pulses, communicates over a wireless link using UWB antennas and a wideband direct conversion front-end, and samples the received signal for demodulation. Design considerations are introduced for a custom chipset that operates in the 3.1-10.6 GHz band. The chipset is being designed using the results from the discrete prototype.

Low-Power Impulse UWB Architectures and Circuits

Ultra-wide-band (UWB) communication has a variety of applications ranging from wireless USB to radio frequency (RF) identification tags. For many of these applications, energy is critical due to the fact that the radios are situated on battery-operated or even batteryless devices. Two custom low-power impulse UWB systems are presented in this paper that address high- and low-data-rate applications. Both systems utilize energy-efficient architectures and circuits. The high-rate system leverages parallelism to enable the use of energy-efficient architectures and aggressive voltage scaling down to 0.4 V while maintaining a rate of 100 Mb/s. The low-rate system has an all digital transmitter architecture, 0.65 and 0.5 V radio-frequency (RF) and analog circuits in the receiver, and no RF local oscillators, allowing the chipset to power on in 2 ns for highly duty-cycled operation.

Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks

In the past few years, wireless microsensor networks have attracted a great deal of attention in the research community. This is due to the applications that will be enabled once wireless microsensor networks are in place. The design of wireless microsensor networks, however, represents a difficult challenge. Since many applications require fault-tolerant, long-term sensing, one important challenge is to design sensor networks that have long system lifetimes. Achieving long system lifetimes is difficult because sensor nodes are severely energy-constrained. In this paper, we demonstrate system-level techniques that adapt and tradeoff software and hardware parameters in response to changes in the requirements of the user, the characteristics of the underlying hardware, and the properties of the environment. By using these power-aware, system-level techniques, we are able to reduce the energy consumption of both general, adaptable systems and dedicated point systems. Moreover, given a specific set of operating conditions for a particular system, we show how energy savings of 50% can be achieved.

A baseband processor for impulse ultra-wideband communications

This paper presents a baseband processor architecture for pulsed ultra-wideband signals. It consists of an analog-to-digital converter (ADC), a clock generation system, and a digital back-end. The clock generation system provides different phases of a 300-MHz clock using four differential inverter stages. The specification of the jitter standard deviation is 100 ps. The Flash interleaved ADC provides four bit samples at 1.2 Gsps. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 65 /spl mu/s. The entire synchronization algorithm is implemented in the digital domain, without feeding any signals back to the clock control. The baseband processor and ADC were implemented on the same 0.18-/spl mu/m CMOS die at 1.8 V as part of a complete baseband transceiver. A wireless data rate of 193 kb/s is demonstrated.

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With

MEMS-based oscillators offer a silicon-based alternative to quartz-based frequency references. Here, a MEMS-based programmable oscillator is presented which achieves better than ±0.5-ppm frequency stability from -40°C to 85°C and less than 1-ps (rms) integrated phase noise (12 kHz to 20 MHz). A key component of this system is a thermistor-based temperature-to-digital converter (TDC) which enables accurate and low noise compensation of temperature-induced variation of the MEMS resonant frequency. The TDC utilizes several circuit techniques including a high-resolution tunable reference resistor based on a switched-capacitor network and fractional-N frequency division, a switched resistor measurement approach which allows a pulsed bias technique for reduced noise, and a VCO-based quantizer for digitization of the temperature signal. The TDC achieves 0.1-mK (rms) resolution within a 5-Hz bandwidth while consuming only 3.97 mA for all analog and digital circuits at 3.3-V supply in 180-nm CMOS.

Frequency Stability and

This paper presents a direct-conversion receiver for FCC-compliant ultra-wideband (UWB) Gaussian-shaped pulses that are transmitted in one of fourteen 500-MHz-wide channels within the 3.1-10.6-GHz band. The receiver is fabricated in 0.18-mum SiGe BiCMOS. The packaged chip consists of an unmatched wideband low-noise amplifier (LNA), filter, phase-splitter, 5-GHz ISM band switchable notch filter, 3.1-10.6-GHz local oscillator (LO) amplifiers, mixers, and baseband channel-select filters/buffers. The required quadrature single-ended LO signals are generated externally. The average conversion gain and input P1dB are 32 dB and -41 dBm, respectively. The unmatched LNA provides a system noise figure of 3.3 to 5 dB over the entire band. The chip draws 30 mA from 1.8 V. To verify the unmatched LNAs performance in a complete system, wireless testing of the front-end embedded in a full receiver at 100 Mbps reveals a 10-3 bit-error rate (BER) at -80 dBm sensitivity. The notch filter suppresses out-of-band interferers and reduces the effects of intermodulation products that appear in the baseband. BER improvements of an order of magnitude and greater are demonstrated with the filter

Integrated Jitter

This paper presents a baseband processor for pulsed ultrawideband signals. It consists of an analog to digital converter (ADC), a clock generation system and a digital back-end. The FLASH interleaved ADC provides four bit samples at 1.2 GSPS. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 70 /spl mu/s. The baseband processor was implemented in the same 0.18 /spl mu/m CMOS chip as a part of a complete transceiver. A complete 193 kbps wireless link is demonstrated.

A BiCMOS Ultra-Wideband 3.1–10.6-GHz Front-End

A custom UWB transceiver chipset is presented that communicates in three 550 MHz-wide channels in the 3.1 to 5 GHz band by using pulse position modulation (PPM). The transmitter uses an all-digital architecture and calibration technique to synthesize pulses with programmable width and center frequency. No analog bias currents or RF oscillators are required in the transmitter. The receiver performs channel-selection filtering, energy detection, and bit-slicing. The receiver circuits operate at 0.65 V and 0.5 V, and can turn on in 2 ns for duty-cycled operation. The two chips are fabricated in a 90 nm CMOS process, and achieve a combined 2.5 nJ/bit at a data rate of 16.7 Mb/s.