Frédéric Goutti

A phase-shift self-oscillating stereo class-D amplifier for battery-powered applications

This paper presents a highly efficient stereo audio amplifier, based on a self-oscillating modulator. This modulation scheme has been analyzed and shows to have a higher bandwidth and error correction than standard Pulse Width Modulation (PWM). A practical implementation in CMOS 0.25um technology has been done to validate our theoretical and simulation results, based on a modified PWM amplifier. Our amplifier demonstrated a Total Harmonic Distortion plus Noise (THD+N) as low as 0.007%, current consumption is 3.88mA at 3.6V (stereo) and the efficiency reaches 88% into 8Ohms. The integrated circuit measures 1.6×1.6mm and is able to work at supply voltages from 2.3V to 5.5V.

A high PSRR Class-D audio amplifier IC based on a self-adjusting voltage reference

In a wide range of applications, audio amplifiers require a large Power Supply Rejection Ratio (PSRR) that the current Class-D architecture cannot reach. This paper proposes a self-adjusting internal voltage reference scheme that sets the bias voltages of the amplifier without losing on output dynamics. This solution relaxes the constraints on gain and feedback resistors matching that were previously the limiting factor for the PSRR. Theory of operation, design and IC evaluation in a Class-D amplifier in CMOS 0.25µm will be shown in this paper. The use of this voltage reference increased the amplifiers PSRR by 15dB, with only a 140µA increase in current consumption.

A class D headphone amplifier with DC coupled outputs and 1.2mA quiescent current

This paper shows the design of a headphone amplifier using Pulse Width Modulation (PWM) to improve its power efficiency compared to existing Class AB and Class G structures. A numerical optimization of the switching frequency and output transistors size, combined with the use of a soft switching scheme, brought the current consumption down to 1.2mA at idle for the complete stereo amplifier. The outputs are DC coupled, with no common mode voltage, thanks to the use of a Negative Charge Pump (NCP). Theory of operation, optimization, and the design in a 0.25μm CMOS process will be explained.

Improved Class-K amplifier for headset applications

This paper proposes an improved Class-K audio amplifier as an alternative solution to Class-AB and Class-G audio amplifiers for Headset applications. The Class-K architecture consists in a linear and a switching amplifier connected in parallel to the same speaker. The advantage of this solution is to associate the power efficiency of the switching amplifier with the linearity of a linear amplifier. However, the Class-K may suffer from static consumption. Three methods are presented in order to compensate the topologys disadvantages: a ternary modulation, a two-stage linear amplifier and a low idle switching amplifier. In this paper, we present the Class-K operating principle, a topological comparison and solutions to improve high static consumption. The simulation results prove the validity of these solutions, achieving less than 2mA of static current.

Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology

A radiation-hardening technique for a CMOS voltage reference circuit is proposed. Its operation principle consists in combining linearly two different NMOS threshold voltages and a Proportional-To-Absolute-Temperature (PTAT) voltage, which allows the compensation of both temperature-induced and radiation-induced discrepancies. This circuit was implemented in a standard 130 nm CMOS technology and designed in two different layouts. Measurements show a good operation with a minimal supply voltage of 2.5 V, a PSRR of 80 dB at 3.3 V. The voltage output shift is around 0.5% under irradiation up to 40 krad(Si). The active area of the circuit is about 0.04 mm2.

Radiation-Hardened Low-Level Offset Operational Amplifiers

Continuous-time auto-zero and ping-pong operational amplifiers dedicated to space applications are proposed. The circuits were implemented in a standard 130 nm CMOS technology. They have been irradiated to evaluate their low-dose-rate radiation sensitivity. Measurement results show that these architectures can provide an input offset voltage lower than 1 μV. Comparisons with commercial low offset amplifiers are made to show the interest of the auto-offset cancellation for space applications.

Design of a TID-tolerant low-level offset operational amplifier

An auto-zero operational amplifier dedicated to space applications is proposed. Its operation principle is based on a continuous-time auto-zeroed amplifier topology to provide a low-level offset. The circuit was implemented in a standard 130 nm CMOS technology. Simulations show that the residual offset is reduced to a few microvolts. The gain bandwidth product is estimated at 10 MHz, and the slew-rate at 7 V/μs for a load capacitor of 10 pF. The current supply is about 300 μA.