Hervé Lapuyade

Backside laser testing of ICs for SET sensitivity evaluation

A new experimental approach combining backside laser testing and analog mapping is presented. A new technique for integrated circuits (ICs) backside preparation by laser ablation is evaluated. The methodology is applied to the study of single-event transient (SET) sensitivity on a linear IC.

Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA

A self-testable and highly reliable low noise amplifier designed in 0.13 m CMOS technology is presented in this paper. This reliable LNA could be used to design the front-end of critical nodes in wireless local area networks to ensure data transmission. The LNA test, based on a built-in self test methodology, monitors its behavior. The test circuit is composed of one sensor and one biasing voltage sensor, and it offers high fault coverage. The high reliability is ensured by the use of redundancies. The LNA works under a 0.9 V supply voltage and the test chip has RF characteristics suitable for 802.11b/g applications. Parametric faults are injected and detected to demonstrate the efficiency of the BIST circuitry. Thanks to the switching on redundant blocks, performances are maintained and hence this proves the reliability of the methodology proposed.

Backside SEU laser testing for commercial off-the-shelf SRAMs

This paper presents a new methodology for single-event upset laser testing of commercial off-the-shelf SRAMs. This methodology is based on backside laser test and is illustrated with some experimental results obtained with a new dedicated laser test bench.

Validation of radiation hardened designs by pulsed laser testing and SPICE analysis

Abstract A new pulsed laser system dedicated to the simulation of radiation effects on integrated circuits is presented. On-line testing capabilities are detailed and two SPICE models of radiation induced transient currents are proposed to be used for results analysis.

Laser cross section measurement for the evaluation of single-event effects in integrated circuits

Abstract The cross section of ICs extracted from particles accelerator testing is extended to the pulsed laser testing. The extraction methodology attached to this new parameter is presented. It provides a new tool for integrated circuits reliability quantification, illustrated in the case of SEU sensitivity evaluation of a single SRAM cell.

SPICE modeling of the transient response of irradiated MOSFETs

A new SPICE model of irradiated MOSFET taking into account the real response of the four electrodes is proposed. A comparison between SPICE-generated transient response and PISCES device simulation demonstrates the accuracy benefits when used in complex electronic architectures.

A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications

An otherwise well-known ratiometric built-in current sensor (BICS) dedicated to monitor the current of analog and mixed-signal building blocks highlights a dependency with regards to technology discrepancy. In this paper we present a design methodology that allows to dramatically reduce the dependency, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the BICS proposed has a peak-to-peak dispersion lower than 10 % of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self test methodology is illustrated by monitoring the supply current of a low-noise amplifier (LNA). Measurements confirm the BICSs low sensitivity to process variations and its transparency relative to the circuit under test (CUT)

An overview of the applications of a pulsed laser system for SEU testing

This paper presents several recent results concerning single-event upset testing with a pulsed laser. It includes sensitivity mapping of an test SRAM cell, slave-induced upset in a flip-flop, MBU mapping of a 16 Mbit DRAM, and online testing of a sequencer-counter.

Single-event sensitivity of a single SRAM cell

A test vehicle has been specially realized to demonstrate that different physical mechanisms are responsible for single-event upset phenomena within an elementary memory cell, depending on the impact location. Validation is performed using pulsed laser equipment.

A 10GHz Distributed Voltage Controlled Oscillator for WLAN Application in a VLSI 65nm CMOS Process

This work demonstrates the feasibility of a distributed voltage controlled oscillator (DVCO) designed for WLAN applications in a 65 nm CMOS process with standard VLSI backend. This DVCO achieves a tuning range of 1.1 GHz (from 10.6 GHz to 11.7 GHz) and a measured phase noise of -116 dBc/Hz at 1 MHz offset from the carrier. To achieve such performances, the DVCO consumes a DC current of 36 mA from a 2 V power supply.