Colette Morche

Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology

A radiation-hardening technique for a CMOS voltage reference circuit is proposed. Its operation principle consists in combining linearly two different NMOS threshold voltages and a Proportional-To-Absolute-Temperature (PTAT) voltage, which allows the compensation of both temperature-induced and radiation-induced discrepancies. This circuit was implemented in a standard 130 nm CMOS technology and designed in two different layouts. Measurements show a good operation with a minimal supply voltage of 2.5 V, a PSRR of 80 dB at 3.3 V. The voltage output shift is around 0.5% under irradiation up to 40 krad(Si). The active area of the circuit is about 0.04 mm2.

Radiation-Hardened Low-Level Offset Operational Amplifiers

Continuous-time auto-zero and ping-pong operational amplifiers dedicated to space applications are proposed. The circuits were implemented in a standard 130 nm CMOS technology. They have been irradiated to evaluate their low-dose-rate radiation sensitivity. Measurement results show that these architectures can provide an input offset voltage lower than 1 μV. Comparisons with commercial low offset amplifiers are made to show the interest of the auto-offset cancellation for space applications.

Design of a TID-tolerant low-level offset operational amplifier

An auto-zero operational amplifier dedicated to space applications is proposed. Its operation principle is based on a continuous-time auto-zeroed amplifier topology to provide a low-level offset. The circuit was implemented in a standard 130 nm CMOS technology. Simulations show that the residual offset is reduced to a few microvolts. The gain bandwidth product is estimated at 10 MHz, and the slew-rate at 7 V/μs for a load capacitor of 10 pF. The current supply is about 300 μA.