Fu Fangfa

NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing

In this paper, we present an AXI compliant Network Interface (NI) for NoC, which can deal with the reordering problem and support the adaptive routing. On the basic of analyzing the necessity and feasibility of packet reordering, we propose a novel reordering mechanism based on look up table, which can guarantee globally ordering of the response transactions. Our NI (NISAR) also supports the master and slave core together. The average latency introduced by NISAR is 3-4 cycles, and the throughput achieves up to 0.87 flits/cycle for a random transaction length between 1 and 16. The proposed architecture synthesized with TSMC 0.13 um technology and the area of it is 0.28 mm2.

An Objective-Flexible Clustering Algorithm for task mapping and scheduling on cluster-based NoC

An Objective-Flexible Clustering Algorithm (OFCA), which is applicable to multiple design objectives and targets high performance and low energy task mapping and scheduling on homogenous cluster-based NoC, is presented. OFCA employs a lineal clustering to group tasks into clusters, and utilizes an efficient heuristic task mapping process to allocate ready clusters onto the platform. Then a low latency pipeline-based static task scheduling stage is proposed to arrange task sequence in IP cores. Finally a best hardware resource demand for the application could be predicted for reference. OFCA can fully exploit the parallel characteristics within task graphs to minimize inter-cluster communication and limit copying tasks when clustering to reduce extra execution energy. It also controls the use of task-duplication-technique (TDT) by setting different parameters for flexible goals to make a compromise between energy and latency. Experiments show that objectives can be adjusted via different parameter ratios performing OFCA and 57% energy savings on average can be achieved compared to CM Algorithm when employed to streaming applications of 18, 36, and 40 tasks.

A novel communication strategy between PE and NI in NoC-based MPSoC

More and more computing cores will be integrated in the future SoC to deal with the growing application requirement. For such Multi-Processor System-on-Chip (MPSoC) with high integration and large complexity, one key issue is the on-chip communication among various cores. By the way of analyzing the communication process, this paper proves that the bottleneck of inter-core communication is the interaction between computing and communicating element. Targeting high efficiency of such interaction, a novel interaction strategy which combines a Lookup Table (LUT) mechanism and DMA mode, is proposed. In this strategy, a hardware message address table is created in the network interface (NI), and NI can transfer the data from the network to local memory directly by looking up this table. It can remarkably reduce the usage of CPU interruption during communication, which is significant to improve the communication performance. The experimental results show that the proposed strategy brings better performance than the traditional buffer pool strategy when the message size is big, and performs the same when the message size is small.

Fault-tolerant routing method of NoC system based on clustering

Along with the development of semiconductors channel length that narrows toward the deep submicron and even nanometer, the design of SoC has become increasingly complex. Therefore, how to achieve fault tolerance, aiming to avoid the impact process issues and improve reliability of system, has become the focus of the NoC design. This paper presents a fault tolerance routing method on NoC system that can perfectly solve the problems above. Targeted low latency, this method based on the existing deterministic algorithms as well as adaptive algorithms and introduces a router clustering technology which supports task based mapping and feedback. The NIRGAM simulator is utilized to achieve performance evaluation. Experiments show that the proposed method has already achieved the goal that applications keep running on the system without the effect of unexpected faults in the NoC. Besides, the performance of system does not decrease dramatically with the number of faults increasing on the chip.