Lai Feng-chang

Optimal Schemes for ADC BIST Based on Histogram

Two testing time reducing schemes of histogram-based BIST (built-in self test) for testing of ADC IPs (intellectual property) are presented in this paper. The first technique uses parallel time decomposition to minimize not only chip area overhead but also testing time in the ADC BIST based on histogram. The second scheme named fold linear histogram-based BIST is proposed to further reduce testing time during computation of DNL (differential nonlinearity) and INL (integral nonlinearity) with little hardware overhead increase. Pseudo-algorithms are given to derive DNL, INL, offset and gain error. A practical implementation is described and the performance is evaluated

A 64 bit parallel CMOS adder for high performance processors

A fast 64 bit parallel binary adder for high performance microprocessors and DSP processors is described. It is implemented in UMC 2.5 V 0.25 /spl mu/m 1-poly 5-metal CMOS technology. A new adder architecture with four stages of dynamic logic is proposed, based on the modification of Kogge and Stone algorithm. Efficiently using dynamic compound gates, clock-delayed dynamic logic and FET scaling technique, the new adder architecture achieved good performance. The addition latency is 700 ps, 20% faster than that of the conventional architecture adder. The area of the adder is 0.16 mm/sup 2/, similar to that of the conventional one.

Design and implementation of high-speed Reed-Solomon decoder

This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon decoder based on the modified Euclidean algorithm. A new multiplier and inversion for GF(2/sup m/) are implemented on the composite field GF(2/sup 2n/) (m=2n), which offers lower hardware requirements compared to standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, not only decoding latency but also hardware overheads of RS (204,188) decoder is reduced greatly compared to the conventional architecture with the same decoding rate. The complexity of the proposed RS decoder is about 118,000 gates, and the decoding latency is only 220 clock cycles and has a throughput of 800 Mbit/s using 0.25 /spl mu/m CMOS process.

A low-cost BIST scheme for ADC testing

A low-cost BIST scheme based on linear histogram for testing ADC is presented in this paper. A parallel time decomposition technique is presented to minimize not only hardware overhead but also testing time of the BIST scheme based on histogram. An area-efficient linear triangular waveform generator is discussed as test stimulus. The technique uses digital delta-sigma noise shaping to generate the on-chip precise analog stimulus and simplify the analog circuit of the generator at same time. A practical implementation is described and the performance is evaluated

A low dropout regulator with over current reminder circuits

A low voltage, low dropout (LDO) regulator with an over current reminder circuit is proposed in this paper. Based on SMIC 0.18µm mix signal CMOS process, the circuit is able to drive a load up to 120mA, and it can give an over current warning to the customer when the load current is over 120mA, and when the load current drops down to 110mA the warning will be recalled. By using the pole-zero tracking frequency compensation, the ripple of the output voltage between 28mV∼30mV when a current pulse draws-out from the LDO1.

A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation

A capacitor-free CMOS low-dropout (LDO) regulator for system-on-chip (SoC) applications is presented. By adopting AC-boosting and active-feedback frequency compensation (ACB-AFFC), the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.

DC photocurrent rejection of high transimpedance gain preamplifier in infrared wireless optical receiver

A high gain transimpedance preamplifier in the infrared wireless optical receiver is presented. Employing an active inductor as the active cancellation scheme, a novel dc photocurrent rejection technique of a transimpedance amplifier (TIA) is designed to eliminate dc photocurrent generated by ambient light. Implemented in Chartered 0.35µm CMOS technology, the preamplifier provides a transimpedance gain of 120dBΩ and the current sensitivity of 500pA, and achieves to reject the dc photocurrent with the range of 0µA to 20µA. Operating under a 3.3V supply, the power dissipation is 0.6mW1.

The design of AMBA AHB/VCI wrapper

Utilizing a core-centric approach, we can develop plug-compatible components and greatly maximize design reuse. IP blocks and buses with standard core interface can be plugged directly together with little or no custom interfacing, saving an amount of design time. This article presents the design of AMBA AHB/VCI wrapper which is intended for connecting VCI-based cores to the AMBA AHB bus. The paper details the comparison and contrast between the AMBA AHB bus protocol and BVCI interface protocol. The two key techniques: quasi-pipelined operation and pre-fetching is proposed to reduce performance overhead. We also take its configurability into consideration to enhance the flexibility of application. Finally, the paper discusses the practicability of VCI usage with an on-chip bus.Utilizing a core-centric approach, we can develop plug-compatible components and greatly maximize design reuse. IP blocks and buses with standard core interface can be plugged directly together with little or no custom interfacing, saving an amount of design time. This article presents the design of AMBA AHB/VCI wrapper which is intended for connecting VCI-based cores to the AMBA AHB bus. The paper details the comparison and contrast between the AMBA AHB bus protocol and BVCI interface protocol. The two key techniques: quasi-pipelined operation and pre-fetching is proposed to reduce performance overhead. We also take its configurability into consideration to enhance the flexibility of application. Finally, the paper discusses the practicability of VCI usage with an on-chip bus.

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance, this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256 μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64 μA quantization range and a 5 V supply voltage/±256 μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46 dB, DNL/INL are −0.005 to +0.027 LSB/–0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.

VLSI design and implementation of high-speed RS(204,188) decoder

This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon (204,188) decoder based on the modified Euclidean algorithm (MEA). A new multiplier and inversion for GF(2/sup m/) are implemented on the composite field GF(2/sup 2n/) (m = 2n), which offers no more than 75% hardware requirements of the standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, a novel parallel MEA architecture is proposed to reuse the registers and multipliers, which can save about 30% hardware overheads compared to the conventional architecture with the same decoding rate. Using 0.25 /spl mu/m CMOS technology, the complexity of the proposed RS decoder is about 30,000 gates with the decoding latency of 239 clock cycles and a throughput of 1.6 Gbit/s.