Yu Mingyan

NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing

In this paper, we present an AXI compliant Network Interface (NI) for NoC, which can deal with the reordering problem and support the adaptive routing. On the basic of analyzing the necessity and feasibility of packet reordering, we propose a novel reordering mechanism based on look up table, which can guarantee globally ordering of the response transactions. Our NI (NISAR) also supports the master and slave core together. The average latency introduced by NISAR is 3-4 cycles, and the throughput achieves up to 0.87 flits/cycle for a random transaction length between 1 and 16. The proposed architecture synthesized with TSMC 0.13 um technology and the area of it is 0.28 mm2.

An efficient ASIC implementation of SHA-1 engine for TPM

With the development of trusted computing systems, TCG promotes TPM as the core hardware building block. The SHA-1 engine in TPM contributes the performance of the whole platform. In this paper, the data flow latencies of the SHA-1 hardware implementation are analyzed, and the bottlenecks are optimized by special arithmetic structures. As a result, the frequency of the optimized structure has increased by 43%. And the performance of this SHA-1 engine is also compared with other SHA-1 engines by frequency, area and throughput.

Designing AHB/PCI bridge

The PCI Local Bus is a high performance, 32-bit or 64-bit bus with multiplexed address and data lines. It is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards and processor/memory systems. The AHB of AMBA (Advanced Microcontroller Bus Architecture) is also designed for high-performance, high clock frequency system modules. In SoC design, the AHB acts as a high-performance system backbone bus. The function of AHB/PCI bridges is to map various control signals and address spaces from one bus into those of another. This paper presents the design of the AHB/PCI bridge.

A low dropout regulator with over current reminder circuits

A low voltage, low dropout (LDO) regulator with an over current reminder circuit is proposed in this paper. Based on SMIC 0.18µm mix signal CMOS process, the circuit is able to drive a load up to 120mA, and it can give an over current warning to the customer when the load current is over 120mA, and when the load current drops down to 110mA the warning will be recalled. By using the pole-zero tracking frequency compensation, the ripple of the output voltage between 28mV∼30mV when a current pulse draws-out from the LDO1.

Design and implementation of concatenated decoder

A concatenated decoder mainly composed of depunctured Viterbi decoder, convolutional deinterleaver, and Reed-Solomon decoder is presented. It has very wide applications in DVB, HDTV and satellite communication systems. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. The algorithms of Viterbi decoder and RS decoder are modified T-algorithm and modified Euclidean algorithm, respectively. Furthermore, the finite field multipliers and inversion over composite fields was adapted to optimize area and power in RS decoder, which reduced the area near to 25% compared to the conventional finite fields. The proposed concatenated decoder has about 81,000 gates except RAM model, which are implemented in 100 MHz using 0.25 um CMOS process.

A novel piecewise curvature-corrected CMOS bandgap reference

A novel and simple piecewise curvature-corrected bandgap voltage reference (BGR) is proposed. It features in employing temperature-dependent resistor ratio to get a piecewise corrected current, which corrects the nonlinear temperature dependence of the first-order BGR. The piecewise corrected current generator forms a negative feedback to improve the line regulation and power supply rejection (PSR) of the proposed BGR. Simulation result shows the temperature coefficient (TC) of 5ppm/K in the industry temperature range (223-398K) and PSR of -82dB are achieved at 2.6-V supply voltage. The simulated line regulation is 0.6mV/V in the supply range of 2.6V-5.6V. It is designed in SMIC 0.35-mum 5-V n-well digital CMOS process.

A novel current reference with low temperature coefficient in a large temperature range

This paper firstly analyse a principle to realize curvature compensated method for CMOS current reference. The circuit of the current reference with very low temperature coefficient is optimized by adjusting some of given parameters according to simulation results. The designed circuit implemented by SMIC 0.18mum CMOS process, and the simulation results show that the temperature coefficient of the current reference is 9.7ppm/degC in a large temperature range from -100 degC to 130 degC, and the power supply rejection ratio (PSRR) is 80dB at 30kHz

The design of AMBA AHB/VCI wrapper

Utilizing a core-centric approach, we can develop plug-compatible components and greatly maximize design reuse. IP blocks and buses with standard core interface can be plugged directly together with little or no custom interfacing, saving an amount of design time. This article presents the design of AMBA AHB/VCI wrapper which is intended for connecting VCI-based cores to the AMBA AHB bus. The paper details the comparison and contrast between the AMBA AHB bus protocol and BVCI interface protocol. The two key techniques: quasi-pipelined operation and pre-fetching is proposed to reduce performance overhead. We also take its configurability into consideration to enhance the flexibility of application. Finally, the paper discusses the practicability of VCI usage with an on-chip bus.Utilizing a core-centric approach, we can develop plug-compatible components and greatly maximize design reuse. IP blocks and buses with standard core interface can be plugged directly together with little or no custom interfacing, saving an amount of design time. This article presents the design of AMBA AHB/VCI wrapper which is intended for connecting VCI-based cores to the AMBA AHB bus. The paper details the comparison and contrast between the AMBA AHB bus protocol and BVCI interface protocol. The two key techniques: quasi-pipelined operation and pre-fetching is proposed to reduce performance overhead. We also take its configurability into consideration to enhance the flexibility of application. Finally, the paper discusses the practicability of VCI usage with an on-chip bus.

A fast low power embedded cache memory design

A 64 kb cache system designed for 32 bit RISC CPU is realized. The circuits include two 4 ns 32 kb cache memories, two 1.4 ns 64-entry direct mapped translation lookaside buffers (TLB), and two 2 ns 64-lines tagRAM. The high-speed decoder and amplifier are employed. The TLB design contains a line encoder and valid bits with flash clear. This cache memory reduces the power and has faster access time by using the optimized decoder and sense amplifier. SMARCH algorithm makes all the cache system self-testability.

A novel communication strategy between PE and NI in NoC-based MPSoC

More and more computing cores will be integrated in the future SoC to deal with the growing application requirement. For such Multi-Processor System-on-Chip (MPSoC) with high integration and large complexity, one key issue is the on-chip communication among various cores. By the way of analyzing the communication process, this paper proves that the bottleneck of inter-core communication is the interaction between computing and communicating element. Targeting high efficiency of such interaction, a novel interaction strategy which combines a Lookup Table (LUT) mechanism and DMA mode, is proposed. In this strategy, a hardware message address table is created in the network interface (NI), and NI can transfer the data from the network to local memory directly by looking up this table. It can remarkably reduce the usage of CPU interruption during communication, which is significant to improve the communication performance. The experimental results show that the proposed strategy brings better performance than the traditional buffer pool strategy when the message size is big, and performs the same when the message size is small.