Fu-Yen Jian

Developments in nanocrystal memory

Flash nonvolatile memory has been widely applied in portable electronic products. However, traditional flash memory is expected to reach physical limits as its dimensions are scaled down; the charges stored in the floating gate can leak out more easily through a thin tunneling oxide, causing a serious reliability issue. In order to solve this problem, discrete nanocrystal memory has been proposed and is considered to be a promising candidate for the next generation of nonvolatile memories due to its high operation speed, good scalability, and superior reliability. This paper reviews the current status of research in nanocrystal memory and focuses on its materials, fabrication, structures, and treatment methods to provide an in-depth perspective of state-of-the-art nanocrystal memory.

Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor

This letter investigates the degradation mechanism of amorphous indium-gallium-zinc oxide thin-film transistors under gate-bias stress. The larger Vt shift under positive AC gate-bias stress when compared to DC operation indicates that an extra electron trapping mechanism occurs during rising/falling time during the AC pulse period. In contrast, the degradation behavior under illuminated negative gate-bias stress exhibits the opposite degradation tendency. Since electron and hole trapping are the dominant degradation mechanisms under positive and illuminated negative gate-bias stress, respectively, the different degradation tendencies under AC/DC operation can be attributed to the different trapping efficiency of electrons and holes.

Investigating the Drain-Bias-Induced Degradation Behavior Under Light Illumination for InGaZnO Thin-Film Transistors

This letter investigates the effect of gate/drain bias stress in InGaZnO thin-film transistors under light illumination and in a darkened environment. Drain current-gate voltage (ID-VG) as well as capacitance-voltage (C-V) transfer curves are measured to analyze the degradation behavior. The device characteristic exhibits a positively parallel shift after the gate/drain bias stress in the dark. On the other hand, the identical stress performed under light illumination leads to not only a negative shift but also a distortion of the C-V curve in the off state. Such phenomenon can be attributed to hole-trapping-induced barrier lowering near the drain side after illuminated bias stress.

Suppress temperature instability of InGaZnO thin film transistors by N2O plasma treatment, including thermal-induced hole trapping phenomenon under gate bias stress

An abnormal subthreshold leakage current is observed at high temperature, which causes a notable stretch-out phenomenon in amorphous InGaZnO thin film transistors (a-IGZO TFTs). This is due to trap-induced thermal-generated holes accumulating at the source region, which leads to barrier lowering on the source side and causes an apparent subthreshold leakage current. In order to obtain superior thermal stability performance of a-IGZO TFTs, conducting N2O plasma treatment on active layer was expected to avert defects generation during SiO2 deposition process. Reducing defects generation not only suppresses subthreshold current stretch-out phenomenon but also significantly improves the bias stress stability in a-IGZO TFTs at high temperature.

Investigating the improvement of resistive switching trends after post-forming negative bias stress treatment

This paper investigates the improvement of resistive switching trends after post-forming negative bias stress treatment of a Pt/Yb2O3/TiN device that has undergone positive bias forming process for activation. After the treatment, characteristics of the conductive filament, such as the temperature dependence of resistivity and transition mechanism, undergo changes. Furthermore, this treatment causes the conductive filament to transform from being primarily composed of vacancies to being metallic Yb dominant, which not only reduces operation voltages such as Vset and Vreset but also improves the on/off ratio. In reliability tests, the device has stable retention.

On the Origin of Gate-Induced Floating-Body Effect in PD SOI p-MOSFETs

This letter systematically investigates the origin of gate-induced floating-body effect (GIFBE) in partially depleted silicon-on-insulator p-type MOSFETs. The experimental results indicate that GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of negative-bias temperature instability degradation. This can be partially attributed to the electrons tunneling from the process-induced partial n+ polygate. However, based on different operation conditions, we found that the dominant origin of electrons was strongly dependent on holes in the inversion layer under source/drain grounding. This suggests that the mechanism of GIFBE at higher voltages is dominated by the proposed anode electron injection model, rather than the electron valence band tunneling widely accepted as the mechanism for n-MOSFETs.

NBTI Degradation in LTPS TFTs Under Mechanical Tensile Strain

This letter investigates the negative-bias temperature instability (NBTI) degradation of p-channel low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) under mechanical tensile stress. Experimental results reveal that the interface state density Nit and grain boundary trap density Ntrap of tensile-strained LTPS TFTs are more pronounced than those of unstrained LTPS TFTs. Extracted density of states and conduction activation energy Ea both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during NBTI stress. Therefore, NBTI degradation is more significant after tensile strain than in an unstrained condition.

The asymmetrical degradation behavior on drain bias stress under illumination for InGaZnO thin film transistors

This paper investigates behavior of drain bias stress and gate-drain bias stress under illumination for InGaZnO thin film transistors as the current-driver operated. Properties exhibit two-stage degradation behavior during drain bias stress. The photo-excited hole non-uniform trapping from illumination induces drain side barrier lowering and causes an apparent hump phenomenon of the subthreshold swing. However, the positive threshold voltage shift without a hump phenomenon after gate-drain bias stress is different degradation behaviors. It is reliant on whether or not an inversion layer exists in the channel. This work also employs capacitance-voltage measurement to further clarify the mechanism of degradation behaviors.

Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device

This letter studies the nonvolatile memory characteristics of polycrystalline-silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant trap-assisted gate-induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which lies above the gate-to-drain overlap region. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection into the nitride layer. Because the injected hot holes can remain in the nitride layer after repeated Fowler-Nordheim erase and program operations, this method can exhibit good sustainability in such a SONOS-TFT memory device.

Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs

In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the off state. However, our experimental results reveal that the capacitance was related with the leakage current and that it was dependent with the measurement frequencies when operated at the off-state region. The increase of the capacitance value is verified to be due to the increase of the electron capacitance originating from a gate-induced drain-leakage (GIDL) one. Nevertheless, the GIDL-induced electron capacitance can be suppressed by employing band-to-band hot electron stress.