Fumiaki Emoto

Analysis of solid phase crystallization in amorphized polycrystalline Si films on quartz substrates

The solid phase crystallization of amorphized Si films on quartz substances is studied by means of the transmission electron microscope observation of grain growth. The amorphous Si films are prepared by Si ion implantation into polycrystalline Si films deposited by low‐pressure chemical vapor deposition. It has been found that the twin formation in grains at the early stage of the crystallization accelerates the growth rate preferentially in a 〈112〉 direction. During the twin growth about a given 〈112〉 direction, other twins also grow from the twin boundary dendritically in some other 〈112〉 directions, leading to the formation of a large grain of dendritic structure.

A laser-recrystallization technique for silicon-TFT integrated circuits on quartz substrates and its application to small-size monolithic active-matrix LCD's

The laser-recrystallization technique utilizes the connected-island structure for forming recrystallized silicon films with enlarged grain size controlled by the thermal gradient. This technique has been used to fabricate the driver circuits of small-size monolithic active-matrix liquid-crystal displays. A horizontal driver circuit with partially recrystallized silicon thin-film transistors (TFTs) has been successfully fabricated on quartz substrates, together with a vertical driver and active-matrix TFT circuits. The operating frequency of the fabricated horizontal driver circuits can be as high as 10 MHz under a clock voltage of 5 V. >

8 nm Wide Line Fabrication in PMMA on Si Wafers by Electron Beam Exposure

The ultimate limit of electron beam lithography in practical samples, e.g., thick PMMA on bulk Si substrate, was investigated in both experiment and theory. For this, the nanometer electron beam lithography system (NSF-1) was used to perform nanometer structure patterning. Monte Carlo calculation with secondary electron generation included was done to simulate the experiment. Eight nanometer wide lines with 100 nm period were delineated in 230 nm thick PMMA on a bulk Si, probably attaining the ultimate limit of electron beam fabrication. This has also been supported by evaluation based on the Monte Carlo simulation.

A high-voltage polysilicon TFT with multigate structures

An approach is proposed for obtaining a high-voltage thin-film transistor (TFT) with multigate structure where polysilicon TFTs are connected in series. A basic principle for high-voltage operation has been investigated in detail through calculations based on a model describing log I/sub DS/-V/sub GS/ characteristics observed in a single-gate polysilicon TFT. It has been found that off-state (V/sub GS/ >

Solid phase growth technique for high cut-off frequency polysilicon TFT integrated circuits on a quartz substrate

The technique features the use of self-implantation at two energy steps, i.e. 150 and 40 keV. The complete amorphization of the initial low-pressure chemical vapor deposition (LPCVD) polysilicon is thereby attained throughout the film. Application of the solid-phase growth technique resulted in excellent high-frequency performance of the thin-film transistors (TFTs) over a large area with high reproducibility. The field effect mobilities obtained for n-channel and p-channel TFTs are as high as 148 and 68 cm/sup 2//V-s, respectively. TFT shift registers consisting of 223 stages of CMOS D-type flip-flops can successfully operate at clock frequencies up to 25 MHz under a supply voltage of 15.5 V on a fused-quartz substrate. >

Fabrication and resist exposure characteristics of 50 keV nanometer e‐beam lithography system

A 50 keV nanometer e‐beam lithography system was fabricated using a Zr–W thermal field emitter. The system has a beam current ranging from 6×10−12 to 1×10−9 A, a minimum beam spot of 2.4 nm and a scanning field of 240×180 μm2. It was found that the total emission and the specimen current was stable with a fluctuation less than 0.5% for more than 3 h. To investigate nanometer pattern delineation characteristics, the effect of various exposure parameters on a delineated line width were measured and a line pattern with a width less than 20 nm was fabricated. A 40 nm wide one dimensional MOS structure was also fabricated using Ni liftoff and reactive sputter etching techniques.

A CPD image sensor with an SOI structure

A CPD image sensor with an SOI (silicon-on-insulator) structure has been developed. The sensor is composed of read-out transistors fabricated on laser-recrystallized silicon, photodiodes on the seeding region, an MOS shift register, and a CCD shift register. A reproduced image with a 50 (H)*60 (V) pixel image sensor showed reduction of smear noise to a value 1/8000 times that in the bulk transistor as a result of complete isolation of the drains of the read-out transistors by oxide layers. >