Fumihiko Fukunaga

Application of review-SEM to high-resolution inspection for 3xnm nodes

As the pattern size shrinkage, it becomes more important to control the critical size of various pattern shapes at a semiconductor production line. Recently, in a semiconductor process with 20 nm nodes size or less the common optical and even EB inspection tool have considerable limitation to detect critical physical defects. From these backgrounds, we have developed the high-sensitivity fixed point inspection tool based on Review-SEM as the product accomplishment judgment tool for below 10nm size defects on critical size devices. We examined the basic performance of this inspection tool, optimized inspection parameters including beam condition and image processing. Then, the defect detection performance was evaluated using various real advanced memory device containing various critical defects. In this paper, we report these results and show the effectiveness of this inspection tool to the advanced memory devices.

In-die overlay metrology method using defect review SEM images

As device dimensions shrink, the measurement of layer-to-layer overlay is becoming increasingly important. Overlay is currently measured using target patterns fabricated within scribe lines. However, there are residual errors between the measurement values at the scribe lines and the actual values at the circuit pattern regions. Therefore, in-die overlay measurements using circuit patterns are required for precise overlay control. We have developed an in-die overlay measurement method based on SEM images. The overlay is directly measured by comparing a golden image and a test image captured at the circuit pattern region. Each layer is automatically recognized from the images, and the placement error between the two images is determined and used to calculate the overlay. This enables measurement without a specially designed target pattern or the setting up of measurement cursors. In the simulation experiments, the proposed method has linearity and sensitivity for the sub-pixel-order overlay even if the patterns have size variations. The basic performance of this method was evaluated using a defect review SEM. For advanced memory devices, a measurement repeatability of less than 1.0 nm was achieved, and a reasonable wafer map of the overlay was obtained.